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Description: CH2 VHDL 数字电路参考书所有程序2-CH2 VHDL digital circuit two reference books all procedures
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Size: 134144 |
Author: 胡计划 |
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Description: VHDL 8位无符号除法器 试验报告
计算前在A和B端口输入被除数和除数,然后在Load线上送高电平,把数据存到除法计算电路内部,然后经过若干个时钟周期,计算出商和余数,并在C和D端输出。
其实现方法是,将除法器分为两个状态:等待状态与运算状态。
开始时除法器处于等待状态,在该状态,在每一时钟上升沿,采样Load信号线,若是低电平,则仍处于等待状态,如果采样到高电平,除法器读取A,B数据线上的输入数据,保存到内部寄存器a_r,b_r,置c_r为0,d_r为a_r,判断除数是否为零,若不为零则进入运算状态。
-VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
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Size: 82944 |
Author: aa |
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Description: 用VHDL编写的一个闹钟的控制程序,希望大家看了后能喜欢,也可以学学哟!-VHDL prepared an alarm clock control procedures in the hope that everyone will love after reading them, but also can learn yo!
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Size: 1024 |
Author: lw |
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Description: 一个16位cpu的vhdl代码。具体内容我也不清楚,自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
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Size: 3072 |
Author: 王林 |
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Description: HDB3编码器 使用VHDL编制 对于基带传输很有用的程序-HDB3 encoder using VHDL preparation for baseband transmission useful procedure
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Size: 1024 |
Author: ls |
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Description: msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures
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Size: 4096 |
Author: 王剑 |
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Description: ask psk 编码调制的vhdl 实现-ask psk coded modulation to achieve the VHDL
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Size: 72704 |
Author: 王发 |
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Description: 有关 VHDL进行VGA显示的源程序,请大家好好参考-VHDL for the VGA display the source code, please make reference to
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Size: 27648 |
Author: 111 |
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Description: 在数字电路中,常需要对较高频率的时钟进行分频操作,得到较低频率的时钟信号。我们知道,在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
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Size: 5120 |
Author: 王力 |
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Description: VHDL编写的自动售货机,带找零、退币功能,数字电路课程设计!内附常态图,和dofile波形模拟文件-VHDL prepared by the vending machines, have sought to bring, the coin features, digital circuit design courses! Enclosing normal map and document dofile waveform simulation
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Size: 3072 |
Author: 张傻 |
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Description: VHDL编写的交通灯程序,有倒计时功能,数字电路课程设计,内附状态图和dofile波形模拟!-VHDL prepared by the traffic lights procedures, the countdown function, digital circuit design courses, enclosing a state map and dofile waveform simulation!
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Size: 4096 |
Author: 张傻 |
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Description: VHDL写的51单片机内核,实现51的全部工能,学习开发FPGA的参考资料。-VHDL wrote 51 microcontroller core, the realization of all the 51 workers may learn FPGA development of reference materials.
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Size: 95232 |
Author: 杨标 |
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Description: ALTERA NIOS处理器实验,QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
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Size: 1024 |
Author: 秦拣俭 |
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Description: vhdl 很好用于串行通信.
三个模快,发生时钟,发送和
接收过程-VHDL good for serial communication. Three die fast, occurred clock, sending and receiving process
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Size: 124928 |
Author: 刘三 |
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Description: des vhld 源码 程序完成了DES的编码和解码功能-des vhld source procedures completed DES encoding and decoding
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Size: 5120 |
Author: 王亮 |
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Description: -- PCI Target Interface Design for XC73144 --
-- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144---- Synopsys VHDL Solution using Xilinx XC7000 Library
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Size: 3072 |
Author: processor |
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Description: 步进电机控制,控制器,控制电机的VHDL源程序-stepper motor control, controllers, motor control VHDL source
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Size: 1024 |
Author: 刘 |
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Description: dds的vhdl实现,主要包括正弦波、三角波和锯齿波的产生-dds achieve the VHDL, including sine, triangle wave, and the selection ramp
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Size: 1024 |
Author: xxx |
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Description: vga 程序
demo程序,可以用,线条显示
可编程逻辑设计vhdl语言编写-vga procedures demo procedures can be used, the lines show programmable logic design, VHDL language
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Size: 310272 |
Author: 冯 理 |
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Description: VHDL的显示驱动程序,VHDL的PS2键盘驱动程序-VHDL display drivers, VHDL PS2 Keyboard Driver
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Size: 3072 |
Author: 张明凯 |
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