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[Other] 基于FPGA的全数字锁相环设计

Description: 用vhdl编写的基于fpga的数字频率计程序算法-prepared using VHDL they simply based on the number of procedures Cymometer Algorithm
Platform: | Size: 286720 | Author: 黄开通 | Hits:

[Communication] uart_verilog

Description: verilog & vhdl以及外国公司的应用说明。-Verilog
Platform: | Size: 148480 | Author: 丁路杰 | Hits:

[VHDL-FPGA-Verilog] alu_inverter

Description: 4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
Platform: | Size: 18432 | Author: bob | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237

Description: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Platform: | Size: 207872 | Author: 上面的 | Hits:

[VHDL-FPGA-Verilog] 66_FIR

Description: 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
Platform: | Size: 8192 | Author: 佴立峰 | Hits:

[VHDL-FPGA-Verilog] 用VHDL实现布斯算法

Description: 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me.
Platform: | Size: 2048 | Author: 刘于 | Hits:

[VHDL-FPGA-Verilog] Sparc_leon_VHDL

Description: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Platform: | Size: 1873920 | Author: 韩红 | Hits:

[VHDL-FPGA-Verilog] 8051inVHDL

Description: 一个8051的VHDL代码，可完整编译，但不保证版图映射成功，可作为设计微处理器的参考-a 8051 VHDL code can be compiled integrity, but it does not guarantee success territory mapping, the microprocessor can be used as a reference design
Platform: | Size: 162816 | Author: 韩红 | Hits:

[VHDL-FPGA-Verilog] VHDL_100Examples

Description: 北京里工大学ASIC设计研究所的100个 VHDL程序设计例子-Beijing University Institute of ASIC design hundred examples of VHDL Design
Platform: | Size: 198656 | Author: 韩红 | Hits:

[VHDL-FPGA-Verilog] tbcpu8bit2

Description: 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
Platform: | Size: 205824 | Author: 冰激凌 | Hits:

[VHDL-FPGA-Verilog] conv_code

Description: 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3)- Convolutional Codes.
Platform: | Size: 1024 | Author: 武汉 | Hits:

[Other] 89_full_adder

Description: 这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.-into first place with the addition of VHDL code more complicated, just for reference.
Platform: | Size: 20480 | Author: 李乐雅 | Hits:

[Other] 1.6运算器部件实验：乘法器

Description: 这个是用vhdl编写的乘法器,仅仅供大家参考-VHDL prepared by the multiplier, just for reference
Platform: | Size: 149504 | Author: 李乐雅 | Hits:

[Other] 1.7运算器部件实验：除法器

Description: 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
Platform: | Size: 151552 | Author: 李乐雅 | Hits:

[VHDL-FPGA-Verilog] booth_mul

Description: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Platform: | Size: 19456 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] 加法

Description: 测试向量波形产生：VHDL实例---加法器源程序 -test vector Waveform Generator : VHDL example-- Adder source
Platform: | Size: 2048 | Author: 张洪 | Hits:

[Communication] crc上传程序

Description: 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
Platform: | Size: 706560 | Author: cdl | Hits:

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