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[VHDL-FPGA-Verilog] music_Code

Description: 音乐编辑与播放设计，采用VHDL编程，用ISE开发工具-music editing and playback design using VHDL programming, development tools with ISE
Platform: | Size: 2048 | Author: 赵晗 | Hits:

[VHDL-FPGA-Verilog] ps2_Code

Description: ps2接口编程实验，采用VHDL编程，用ISE开发工具-ps2 interface programming experiments using VHDL programming, development tools with ISE
Platform: | Size: 6144 | Author: 赵晗 | Hits:

[VHDL-FPGA-Verilog] i2c_control

Description: 本文件是iic总线控制器的vhdl语言的源代码程序-2005/09 Bus Controller VHDL language source code procedures
Platform: | Size: 7168 | Author: 王立华 | Hits:

[VHDL-FPGA-Verilog] state_classic

Description: 用VHDL语言编写的语言,可以利用MODELSIM进行仿真.对于初学者,则更有参考价值.-prepared using the VHDL language, we can use MODELSIM simulation. For beginners, the more valuable reference.
Platform: | Size: 1024 | Author: 徐荣网 | Hits:

[VHDL-FPGA-Verilog] divded-VHDL

Description:
Platform: | Size: 3072 | Author: 林海 | Hits:

[VHDL-FPGA-Verilog] CK20-VHDL

Description: 经典ＣＫ２０时钟程序，实现了时钟的时，分，秒记数，并可以重调，置０-classic procedures CK20 clock and realized the clock, minute and second count, and can be re-emphasize that the Home 0
Platform: | Size: 4096 | Author: 林海 | Hits:

[VHDL-FPGA-Verilog] hanbaosram

Description: 德国汉堡大学的SRAM测试代码,使用VHDL编写,供大家参考-University of Hamburg, Germany, SRAM test code, the use of VHDL, for your reference
Platform: | Size: 6144 | Author: 汪涌 | Hits:

[VHDL-FPGA-Verilog] fir_filter

Description: 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
Platform: | Size: 3072 | Author: li | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
Platform: | Size: 87040 | Author: 黎明 | Hits:

[ARM-PowerPC-ColdFire-MIPS] jtag_cpld_vhdl

Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。 以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。 -JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: | Size: 2048 | Author: 李伟 | Hits:

[VHDL-FPGA-Verilog] 100Examples

Description: 有关于VHDL举例,FPGA/CPLD的运用方面的例子-for example VHDL, FPGA/CPLD to the use of the example
Platform: | Size: 198656 | Author: 许宏亮 | Hits:

[VHDL-FPGA-Verilog] fpga-example1

Description: 集中了十几个vhdl经典程序,如lcd,led控制程序和多种接口程序-focus of a dozen VHDL classic procedures, such as LCD, led control procedures and multiple interface program
Platform: | Size: 66560 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] fpga-example2

Description: ASK调制与解调VHDL程序及仿真 FSK调制与解调VHDL程序及仿真 PSK调制与解调VHDL程序及仿真 基带码发生器程序设计与仿真 频率计程序设计与仿真-ASK modulation and demodulation VHDL simulation procedures and FSK modulation and demodulation process and VHDL simulation PSK modulation and demodulation process and VHDL simulation baseband code generator program design and simulation Cymometer program design and simulation
Platform: | Size: 618496 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] PL_FSK

Description: 数字通信系统通信系统调制解调（PL_FSK）VHDL建模，包括发送和接受模块-Digital Communication System Communication System modulation and demodulation (PL_FSK) VHDL modeling, including sending and receiving modules
Platform: | Size: 187392 | Author: 万金油 | Hits:

[Other Embeded program] vhdlshuzilvbo

Description: 用vhdl实现数字频率的毕业设计！doc文档中有源程序。可以实现功能！-using VHDL digital frequency of the graduate design! Doc is the source document. Functions can be achieved!
Platform: | Size: 165888 | Author: jovi | Hits:

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] VHDL3

Description: 这是一个自动售货机的vhdl源码，曾经是eda比赛的题目，供大家参考。-This is a vending machine in VHDL source code, the game had been sown topic, for your reference.
Platform: | Size: 534528 | Author: | Hits:

[Other] VHDLProgrammingbyExample4thEd

Description: 开发硬件的朋友们注意了，这是最新的VHDL编程书籍。里面有大量实用技巧及程序。-hardware attention to the friends, which is the latest VHDL programming books. There are a lot of practical skills and procedures.
Platform: | Size: 1784832 | Author: 孙刚 | Hits:

[Other] 0809

Description: 0809控制器程序 VHDL编写的 仅供参考-0809 controller procedures prepared by the VHDL is for reference only
Platform: | Size: 2048 | Author: zhangbin | Hits:

[VHDL-FPGA-Verilog] Booth_Multiplier

Description: 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Platform: | Size: 1024 | Author: 韓堇 | Hits:
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