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[VHDL-FPGA-Verilog] 数字系统设计教程4_9

Description: vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
Platform: | Size: 244736 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] 数字系统设计相关

Description: 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
Platform: | Size: 45056 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] 1111078805

Description: VHDL使用例子，包括走马灯，路灯，天线，电子表，数字频率计等-examples of the use of VHDL, including merry-go-round, street lamps, antennas, electronic watches, digital frequency meter, etc.
Platform: | Size: 446464 | Author: 兔八哥 | Hits:

[VHDL-FPGA-Verilog] I2C_IPcore_VHDL

Description: 这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核，可直接编译运行-I2C serial data communication protocol to VHDL hardware description language of the IP core can be directly translated Operation
Platform: | Size: 6144 | Author: 陈州徽 | Hits:

[VHDL-FPGA-Verilog] 状态机设计

Description: 详细说明状态机的设计，用VHDL实现，是不错的教程-detailed state machine design, VHDL, is a good guide
Platform: | Size: 113664 | Author: wl | Hits:

[VHDL-FPGA-Verilog] ddsVHDL

Description: 基于VHDL的DDS设计，在QUTURS2zhon仿真通过-based on the DDS VHDL design and simulation through the QUTURS2zhon
Platform: | Size: 97280 | Author: wl | Hits:

[VHDL-FPGA-Verilog] frequency_counter_2(successful)(top-down design).r

Description: 小巧的频率计数器，VHDL源代码和仿真文件具全，直接从管工程文件拷贝过来。绝对可用。-compact frequency counters, VHDL source code and simulation with all documents directly from the control engineering documents copied. Absolutely available.
Platform: | Size: 126976 | Author: wl | Hits:

[VHDL-FPGA-Verilog] 一个8位处理器结构，源码分析

Description: 关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试-on an eight processors, and source code, VHDL design, the test
Platform: | Size: 92160 | Author: wl | Hits:

[VHDL-FPGA-Verilog] 流水灯VHDL程序

Description:
Platform: | Size: 1024 | Author: 韦元龙 | Hits:

[Driver Develop] 16fft

Description: 用VHDL语言编写的FFT程序，有些参考价值哦-VHDL prepared by the FFT procedure, some reference value oh
Platform: | Size: 655360 | Author: 李利 | Hits:

[DSP program] 基于FPGA的数字信号显示系统软硬件设计

Description: 该文阐述了现场可编程逻辑器件FPGA的主要特点，应用FPGA芯片和VHDL硬件描述语言设计的模拟示波器数字信号显示系统的设计原理和设计方法。-this paper, the field programmable logic devices FPGA main feature FPGA chip and VHDL hardware description language design analog signals to digital oscilloscope system design principles Design and Methods.
Platform: | Size: 439296 | Author: 张志华 | Hits:

[VHDL-FPGA-Verilog] DEMO22

Description: ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ　环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
Platform: | Size: 598016 | Author: liu | Hits:

[VHDL-FPGA-Verilog] autosellmachine

Description: 用VHDL语言编写的自动售货机程序，下载到EDA实验板上可实现基本的买货售货找零显示总钱等功能。-VHDL prepared by the vending machine procedures, Experimental downloaded to EDA board can achieve basic placing orders showed total sales through irregular money functions.
Platform: | Size: 229376 | Author: 木林森 | Hits:

[VHDL-FPGA-Verilog] maxshiyan

Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: | Size: 865280 | Author: 田晶昌 | Hits:

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

Description: 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
Platform: | Size: 3072 | Author: 张云鹏 | Hits:

[Windows Develop] autoring

Description: 用VHDL编的一个实用自动打铃系统，EDA课设的一个经典题目源程序-VHDL a series of practical automatic bell system, EDA of a class-based source classic title
Platform: | Size: 1031168 | Author: 梁露露 | Hits:

[VHDL-FPGA-Verilog] FIRvhdl

Description: 用vhdl实现一个fir滤波器设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation- 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
Platform: | Size: 3072 | Author: 达闻西 | Hits:

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