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[Windows Developkey_borad_test

Description: 本程序为VHDL语言编写的键盘置数程序,并用液晶显示-procedures for the preparation of the VHDL language keyboard home several procedures, and using LCD
Platform: | Size: 4096 | Author: tmx | Hits:

[Windows Developise6.3ad0809_test

Description: 本程序为VHDL语言编写的ADC0809的采样程序 并用DA0800恢复-procedures for the preparation of the VHDL ADC0809 the sampling procedures used to restore DA0800
Platform: | Size: 4096 | Author: tmx | Hits:

[Windows Developtest_lcd

Description: 本程序为VHDL语言编写的LMB162液晶程序 -This program shows us how to use VHDL to chontrol LMB162.
Platform: | Size: 2048 | Author: tmx | Hits:

[Windows Developplj

Description: 本程序为VHDL编写的频率计,测频范围从0.1Hz到1G-VHDL procedures for the preparation of the frequency meter, measuring frequency range from 0.1Hz to 1G
Platform: | Size: 7168 | Author: tmx | Hits:

[VHDL-FPGA-Verilogstep_motor

Description: 步进电机控制器,控制电机的VHDL源程序-step motor controller. the vhdl source of step motor controller
Platform: | Size: 310272 | Author: 王天权 | Hits:

[VHDL-FPGA-Verilogjianpan_vhdl

Description: 用VHDL实现的键盘扫描程序 可以稍微修改就可使用-using VHDL keyboard scanning procedure can be slightly modified to use
Platform: | Size: 172032 | Author: 金军 | Hits:

[Otherszz0001

Description: 用VHDL语言写的一个8位动态扫描显示的时钟程序,数码管的片选须接一个3-8译码器。-VHDL83-8
Platform: | Size: 1024 | Author: 曹海学 | Hits:

[VHDL-FPGA-Verilogkey_scan

Description: 程序主要是用硬件描述语言(VHDL)实现: 4*4键盘扫描,简洁明了,通俗易懂,比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
Platform: | Size: 308224 | Author: 刘赛 | Hits:

[VHDL-FPGA-Verilogmcs_51_cpld

Description: 程序主要用硬件描述语言(VHDL)实现: 单片机与FPGA接口通信的问题-procedures major hardware description language (VHDL) to achieve : MCU and FPGA interface communication problems
Platform: | Size: 150528 | Author: 刘赛 | Hits:

[VHDL-FPGA-Verilogpinglvhecheng

Description: 程序用VHDL实现: 频率合成,DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
Platform: | Size: 145408 | Author: 刘赛 | Hits:

[VHDL-FPGA-Verilog除法器

Description: 通过用硬件描述语言(VHDL)描述除法器,并进行模拟验证,加深对二进制数运算方法的理解。 设计平台:MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
Platform: | Size: 50176 | Author: johnmad | Hits:

[SCMvhdl_lcd

Description: 使用C语言与VHDL实现 液晶显示控制器示例使用说明 使用模块有:单片机模块、液晶显示模块。 使用步骤: 1. 打开电源+5V。 2. 信号连接,按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线,并将程序加载。 4. 液晶屏上将显示一幅图像。 -use C language and VHDL LCD controller using examples of the use of modules : SCM modules, LCD display modules. Use steps : 1. Turn the power 5V. 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connections and will be loading procedures. 4. LCD screen will show an image.
Platform: | Size: 39936 | Author: 刘浪 | Hits:

[VHDL-FPGA-Verilogddsall

Description: DDS的vhdl语言源程序实现 该程序可实现1HZ频率步进-DDS source VHDL language to achieve the program can be realized 1HZ frequency Step
Platform: | Size: 1024 | Author: 欧阳 | Hits:

[Graph programjpeg_src

Description: 是jpeg标准下图象压缩的vhdl实现工程,包括core文件,测试文件,工程文件-image compression vhdl realization project under standard jpeg.core files, test files and project files are included.
Platform: | Size: 1569792 | Author: 石伟 | Hits:

[Other7seg

Description: 七段数码显示程序 VHDL 开发环境为Xilinx 的集成开发工具ISE-VHDL digital display program development environment for Xilinx ISE Integrated Development Tools
Platform: | Size: 1024 | Author: imljg | Hits:

[SCMVHDL范例

Description: 最高优先级编码器 8位相等比较器 三人表决器(三种不同的描述方式) 加法器描述 8位总线收发器:74245 (注2) 地址译码(for m68008) 多路选择器(使用select语句) LED七段译码 多路选择器(使用if-else语句) 双2-4译码器:74139 多路选择器(使用when-else语句) 二进制到BCD码转换 多路选择器 (使用case语句) 二进制到格雷码转换 双向总线(注2) 汉明纠错吗译码器 三态总线(注2) 汉明纠错吗编码器 解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[Communication用cpld实现曼彻斯特编码2

Description: 此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。-this procedure code decoder VHDL hardware is used to prepare the language.
Platform: | Size: 3072 | Author: 游畅 | Hits:

[File Format用VHDL实现查找表方式的FIR滤波器

Description: 这些是我所看到的一些资料,希望与大家分享。也许对您用处不大,但我是一片诚意-these are what I saw in some of the information and hope to share with you all. Perhaps your little usefulness, but I was a sincerity
Platform: | Size: 144384 | Author: yin | Hits:

[File Format基于VHDL与CPLD器件的FIR数字滤波器的设计

Description: 这是我看到的一些资料,希望与大家分享。也许这对您用处不大,但是我的一份诚意。-this is that I see some of the information and hope to share with you all. This may be less useful to you, but my sincerity.
Platform: | Size: 102400 | Author: yin | Hits:

[VHDL-FPGA-VerilogLCD显示实验

Description: ALTERA NIOS处理器,用VHDL在QUARTUS下编写,用NIOS SHELL调试通过,实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
Platform: | Size: 35840 | Author: xf | Hits:
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