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[VHDL-FPGA-Verilog] dds正弦发生器代码

Description: 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Platform: | Size: 491520 | Author: czy | Hits:

[VHDL-FPGA-Verilog] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309248 | Author: czy | Hits:

[VHDL-FPGA-Verilog] DW8051

Description: 大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51
Platform: | Size: 664576 | Author: 李无志 | Hits:

[VHDL-FPGA-Verilog] i2c_cores

Description: IIC总线协议，VHDL语言编写，可以直接使用-IIC bus protocol, VHDL language can be used directly
Platform: | Size: 20480 | Author: 李无志 | Hits:

[VHDL-FPGA-Verilog] manchester_verilog

Description: 这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
Platform: | Size: 9216 | Author: 李无志 | Hits:

[Communication] 伪随机序列

Description: 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and circuit schematics. Procedures can run on platforms win98/2000/NT
Platform: | Size: 162816 | Author: 夏沫 | Hits:

[VHDL-FPGA-Verilog] NO_2_ColorLight

Description: 这个是vhdl的彩灯实例程序，里面涵盖了48种的彩灯变化，通过了maxplus的验证，并且在机上实验通过-this is the Lantern example VHDL procedures inside covers 48 species of Carnival changes adopted maxplus certification, and the plane through experiments
Platform: | Size: 103424 | Author: 何蓥 | Hits:

[VHDL-FPGA-Verilog] flash接口控制_verilog

Description: flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
Platform: | Size: 870400 | Author: 李楠 | Hits:

[VHDL-FPGA-Verilog] 减法计数器

Description: EDA常用计数函数VHDL程序设计，减法计数器：可预置数：-common counting function EDA VHDL programming, subtraction counter : Preset :
Platform: | Size: 3072 | Author: 李培 | Hits:

[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[Other] 三人表决器（三种不同的描述方式）

Description: 用VHDL语言编写的三人表决器，多数服从少数，或者一致通过。-VHDL prepared by the three voting machines, most of the views of the minority, or adopted unanimously.
Platform: | Size: 1024 | Author: 刘超 | Hits:

[Communication] 异步通信控制器

Description: 用VHDL语言编写的异步通信控制器源代码程序-ASCC Communication Control System Compiled With VHDL
Platform: | Size: 346112 | Author: leaf | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Platform: | Size: 111616 | Author: 孙犁 | Hits:

[VHDL-FPGA-Verilog] core_arm.tar

Description: 用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse
Platform: | Size: 655360 | Author: 昭君 | Hits:

[Books] vhdl教程

Description:
Platform: | Size: 1899520 | Author: 刘晓飞 | Hits:

[Other] mp3_decoder

Description: mp3的VHDL实现，包括HUFFMAN编码器，量化器，子带滤波器．可用来开发：ＦＰＧＡ，ＡＳＩＣ．-mp3 of VHDL, including HUFFMAN encoder, quantizer, subband filters. Can be used to develop : FPGA, ASIC.
Platform: | Size: 36864 | Author: 六六 | Hits:

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