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[VHDL-FPGA-Verilog] VGA_Core

Description: 用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.-write VHDL VGA core, is a very good subset of the core, has a lot of functions.
Platform: | Size: 359424 | Author: 朱思华 | Hits:

[VHDL-FPGA-Verilog] VHDL_Programming_by_Example

Description: 本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的教材-Based on the large number of examples of VHDL. For a newcomer it is a very good teaching
Platform: | Size: 1784832 | Author: 林福军 | Hits:

[Other] triffic

Description: 实现得失一个交通灯。利用vhdl语言-realize a gain or loss of traffic lights. The use of VHDL Language
Platform: | Size: 25600 | Author: 流会 | Hits:

[VHDL-FPGA-Verilog] 8255new

Description: vhdl实现8255,可重用，ALATEK公司提供验证，用说明文档-achieve VHDL 8255, reusable, ALATEK companies to provide certification, with documentation
Platform: | Size: 33792 | Author: 昭君 | Hits:

[VHDL-FPGA-Verilog] 8位数字频率计

Description: 数字频率计~ VHDL 实现可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)
Platform: | Size: 657408 | Author: 熊明 | Hits:

[VHDL-FPGA-Verilog] uart from opencores

Description: 用VHDL实现串口可以实现与pc机的通信收发中断都可以效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Platform: | Size: 9216 | Author: 熊明 | Hits:

[VHDL-FPGA-Verilog] config_controller

Description: 用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。-VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.
Platform: | Size: 381952 | Author: lsd | Hits:

[VHDL-FPGA-Verilog] pulse_change

Description: 用vhdl实现脉冲宽度可控的一简单程序仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
Platform: | Size: 183296 | Author: dm | Hits:

[SCM] protel99中文教程

Description: 这是一本学习vhdl语言以及EDA的好书，适合初学者，我强力推荐-This is a learning and EDA VHDL language books, suitable for beginners, I strongly recommend
Platform: | Size: 348160 | Author: 序列 | Hits:

[VHDL-FPGA-Verilog] Game_HLD3

Description: 基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
Platform: | Size: 987136 | Author: 王萌 | Hits:

[VHDL-FPGA-Verilog] Mouse_HLD3

Description: 基于fpga和xinlinx ise的鼠标应用vhdl程序，希望对你有所帮助！-and they simply based on the mouse xinlinx ideally VHDL application procedures, and I hope to help you!
Platform: | Size: 577536 | Author: 王萌 | Hits:

[VHDL-FPGA-Verilog] usbsample

Description: 基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
Platform: | Size: 983040 | Author: 王萌 | Hits:

[VHDL-FPGA-Verilog] PLW

Description: 电子密码锁的vhdl编程实现，不知以前有没有人做过的。-electronic locks VHDL programming, I wonder if the past is not done.
Platform: | Size: 3072 | Author: 王卫 | Hits:

[VHDL-FPGA-Verilog] LED点阵

Description: 大屏幕led点阵显示的驱动时序。使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL description language. Rom which documents can be automatically generated using lpm_megcore.
Platform: | Size: 4096 | Author: 王卫 | Hits:

[VHDL-FPGA-Verilog] color_bar

Description: 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide.
Platform: | Size: 10240 | Author: 石坚 | Hits:

[VHDL-FPGA-Verilog] 自定义逻辑PWM的例子

Description: 是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.
Platform: | Size: 10240 | Author: 石坚 | Hits:

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

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