Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl

Search list

[VHDL-FPGA-Verilog] 7状态机设计

Description: 这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!
Platform: | Size: 5338112 | Author: 振臂 | Hits:

[Data structs] 布斯算法

Description: VHDL实现布斯算法-VHDL Booth algorithm
Platform: | Size: 2048 | Author: 顾静 | Hits:

[VHDL-FPGA-Verilog] IP core

Description: VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
Platform: | Size: 414720 | Author: 周贤 | Hits:

[VHDL-FPGA-Verilog] custom_mul

Description: vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier
Platform: | Size: 1024 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] hdb3 decoder

Description: 我上期做的VHDL设计方案，用于在FPGA或CPLD中实现HDB3的编码-I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Platform: | Size: 119808 | Author: 王薇 | Hits:

[VHDL-FPGA-Verilog] fpga加密设计方法

Description: FPGA加密的方法，对于那些需要加密自己的vhdl源代码的人来说，很有用-FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful
Platform: | Size: 187392 | Author: 陶伟炯 | Hits:

[SCM] mc8051_design

Description: MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core此公司提供的8051 core很容易在FPGA 上用同时也是学习VHDL的一份不错的进阶实例-MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core company for the 8051 core very easy to use in FPGA VHDL is also studying a good example of the SSP
Platform: | Size: 557056 | Author: 寇锐 | Hits:

[VHDL-FPGA-Verilog] DISPLAY-vhdl

Description: vhdl描述的显示代码 maxplus2开发环境-VHDL description of the display code development environment maxplus2
Platform: | Size: 1024 | Author: 丁智罡 | Hits:

[VHDL-FPGA-Verilog] ERFREE_COUNTER-vhdl

Description: maxplus2为开发环境 vhdl编写的自由 计数器 程序-maxplus2 VHDL environment for the development of free counter preparation procedures
Platform: | Size: 12288 | Author: 丁智罡 | Hits:

[VHDL-FPGA-Verilog] SCAN-vhdl

Description: maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program
Platform: | Size: 1024 | Author: 丁智罡 | Hits:

[Other] a VHDL Compiler

Description: 这是一个VHDL（硬件描述语言）的编译器，更确切说是一个解释器，输入是VHDL语言，输出是经过提到后的符号表，也就是将VHDL中的重要变量比如输入输出变量和DFF等保存下来。-This is a VHDL (hardware description language) compiler, more precise explanation is a device that is VHDL input, output was mentioned after the symbol table to VHDL is the important variables such as input and output variables and other DFF preserved.
Platform: | Size: 117760 | Author: gepo | Hits:

[VHDL-FPGA-Verilog] 直流电机控制器

Description: 直流电机控制器，属于精品vhdl源码，可在eda仿真工具上仿真实现-DC motor controller is excellent VHDL source code can be sown in simulation tools Simulation
Platform: | Size: 2048 | Author: 阎磊 | Hits:

[VHDL-FPGA-Verilog] mc8051_cyclone_nios

Description: 增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
Platform: | Size: 2000896 | Author: 柳如飞 | Hits:

[VHDL-FPGA-Verilog] Verilog-golden

Description: VHDL黄金版，本人费了九牛才找到，帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry
Platform: | Size: 203776 | Author: 江涛 | Hits:

[VHDL-FPGA-Verilog] bin27seg_vhdl

Description: 采用VHDL编写的七段数码管显示程序-prepared using VHDL paragraph 107 of the procedures Digital Display
Platform: | Size: 1024 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 一个简单的UART

Description: 采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
Platform: | Size: 3072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] vgaout

Description: VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
Platform: | Size: 7168 | Author: 余飞 | Hits:

[VHDL-FPGA-Verilog] Alu1232

Description: VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
Platform: | Size: 1024 | Author: 张念华 | Hits:

[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[VHDL-FPGA-Verilog] 电子钟clock

Description: 用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
Platform: | Size: 353280 | Author: 刘卫 | Hits:
« 1 2 ... 36 37 38 39 40 4142 43 44 45 46 ... 50 »

CodeBus www.codebus.net