Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl

Search list

[VHDL-FPGA-Verilog] primetime

Description: 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
Platform: | Size: 52224 | Author: 张国梁 | Hits:

[Other] VhdlLanguageReferenceMmanualIEEE1076

Description: vhdl language reference manual IEEE1076(2004.10)-VHDL language reference manual IEEE1076 (2004.10)
Platform: | Size: 1301504 | Author: 谭贤豪 | Hits:

[VHDL-FPGA-Verilog] wodevhdl

Description: vhdl练习实例。在maxplus2中编写，编译通过，正确。-VHDL practice examples. In maxplus2 prepare, compile and correct.
Platform: | Size: 65536 | Author: 梦雨 | Hits:

[VHDL-FPGA-Verilog] Lab_ISE_Led

Description: vhdl实例教程，其中的例子适合新手演示使用，肯定会有帮助的。-VHDL example tutorial, an example of the use for novice demo, it will certainly help.
Platform: | Size: 779264 | Author: ghjghj | Hits:

[VHDL-FPGA-Verilog] wom_kg

Description: 系统时钟的VHDL电路，适合有一定经验的编程人员，希望能对你们有帮助。-VHDL system clock circuit suitable for a certain programming experience, you want to help.
Platform: | Size: 24576 | Author: ghjghj | Hits:

[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] RISC

Description: hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
Platform: | Size: 128000 | Author: 12 | Hits:

[VHDL-FPGA-Verilog] 32fenpinqi

Description: 这是用VHDL语言写的32位分频器的程序，可直接运行，看结果，欢迎使用。多指正，交流。-This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use. More correct exchange.
Platform: | Size: 12288 | Author: 刘彦平 | Hits:

[VHDL-FPGA-Verilog] 44vhdl

Description: 44个vhdl实例 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I/O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-Verilog] hiervhdl

Description: Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-Verilog] clk_divide_3

Description: VHDL语言编写三分频，可以扩展实现任意奇数-VHDL prepared three frequency can be extended to achieve arbitrary odd
Platform: | Size: 124928 | Author: 利津候 | Hits:

[VHDL-FPGA-Verilog] 78_alu_input

Description: vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
Platform: | Size: 2048 | Author: tom | Hits:

[VHDL-FPGA-Verilog] ProgramText

Description: we will use the Spartan3 XC3S200 FPGA to design a specified counter using the language VHDL.-we will use the cables Spartan3 FPGA design to a specified counter using the VHDL language.
Platform: | Size: 12288 | Author: fei | Hits:

[VHDL-FPGA-Verilog] hdb3_VHDL

Description: hdb3 using language VHDL-Indoor using VHDL language
Platform: | Size: 54272 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] 2Dfft

Description: VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.-VHDL design procedures on 2DFFT u scinode1
Platform: | Size: 783360 | Author: 李成 | Hits:

[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[VHDL-FPGA-Verilog] ceshixiangliang

Description: vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples--- corresponding Adder test vector (test bench). Txt
Platform: | Size: 11264 | Author: 陈丽 | Hits:

[Other] full_add

Description: 一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。-a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.
Platform: | Size: 123904 | Author: 陈晓岚 | Hits:

[VHDL-FPGA-Verilog] 12864lcd_vhdl

Description: 12864图形点阵液晶驱动vhdl程序，用ise综合-12864 graphics dot-matrix LCD driver VHDL program, and ideally integrated
Platform: | Size: 9423872 | Author: 赵晗 | Hits:

[VHDL-FPGA-Verilog] vgaCode

Description: VGA动画显示，用VHDL编程，用ise开发-VGA animation, VHDL programming, ideally with development
Platform: | Size: 7168 | Author: 赵晗 | Hits:
« 1 2 ... 44 45 46 47 48 4950 »

CodeBus www.codebus.net