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[Software Engineering] Coursework3

Description: This paper illustrates an approach to design a 4 Quadrant multiplier circuit using BJT. A Quadrant multiplier basically consist of 2 matched differential pair units with BJTs. This principle was established by B.Gilbert in 1968 and the circuit is known as Gilbert’s cell. The operation of BJT and its working as a differential amplifier is explained in brief. Referring to the operation of the differential amplifier as a two quadrant multiplier, the operation of a four quadrant multiplier was analyzed. The basic Gilbert’s cell was simulated using PSpice and improvements were made to increase it linearity of the basic circuit.-This paper illustrates an approach to design a 4 Quadrant multiplier circuit using BJT. A Quadrant multiplier basically consist of 2 matched differential pair units with BJTs. This principle was established by B.Gilbert in 1968 and the circuit is known as Gilbert’s cell. The operation of BJT and its working as a differential amplifier is explained in brief. Referring to the operation of the differential amplifier as a two quadrant multiplier, the operation of a four quadrant multiplier was analyzed. The basic Gilbert’s cell was simulated using PSpice and improvements were made to increase it linearity of the basic circuit.
Platform: | Size: 139264 | Author: Rex | Hits:

[Other] Parallel_Booth_Multiplier

Description: Parallel Booth Multiplier Circuit in VHDL
Platform: | Size: 11264 | Author: Carlos H Nacer | Hits:

[Software Engineering] multi

Description: This a baugh-wooley multiplier verilog code-This is a baugh-wooley multiplier verilog code
Platform: | Size: 139264 | Author: lo-po | Hits:

[VHDL-FPGA-Verilog] lunwen

Description: 潘明海　刘英哲　于维双 (论文) 中文摘要： 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
Platform: | Size: 128000 | Author: culun | Hits:

[VHDL-FPGA-Verilog] cheng1

Description: 用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
Platform: | Size: 26624 | Author: 齐娜 | Hits:

[VHDL-FPGA-Verilog] VHDLbasicExampleDEVELOPEMENTsoursE

Description: 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用，介绍如下： Chapter3：schematic和vhdl文件夹，分别是数字钟设计的原理图文件和VHDL程序； Chapter4：multiplier文件夹，串并乘法器设计程序（提示：先编译程序包）； Chapter5：sci文件夹，串行通信接口设计程序； Chapter6：watchdog文件夹，看门狗设计程序； Chapter7：taxi文件夹，出租车计价器设计程序； Chapter8：elevator文件夹，高层电梯控制器设计程序； Chapter9：cymometer1和cymometer2文件夹，前者是计数测频设计程序，后者是等精度测频设计程序； Chapter10：digital_lock文件夹，数字密码锁设计程序； Chapter11：I2C文件夹，I2C控制器设计程序； Chapter12：fifo文件夹，异步FIFO设计程序； Chapter13：dds文件夹，数字频率合成设计程序； Chapter14：vLA文件夹，虚拟逻辑分析仪设计程序。 -this book includes 12 detail examples of the source program
Platform: | Size: 139264 | Author: wuyu | Hits:

[VHDL-FPGA-Verilog] wallace

Description: This a code for wallace tree multiplier-This is a code for wallace tree multiplier
Platform: | Size: 4096 | Author: vlsi | Hits:

[VHDL-FPGA-Verilog] liushuixian_mul

Description: 流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
Platform: | Size: 3072 | Author: snow | Hits:

[Windows Develop] baughWooleyMultiplier

Description: gate level implementation of 8*8 Signed baugh wooley multiplier!
Platform: | Size: 1024 | Author: Majid | Hits:

[VHDL-FPGA-Verilog] multiplexer

Description: 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
Platform: | Size: 267264 | Author: kk | Hits:

[Other] booth

Description: booth multiplier in verilog, deisgn in parameterized.
Platform: | Size: 25600 | Author: Udit | Hits:

[VHDL-FPGA-Verilog] code

Description: This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
Platform: | Size: 5120 | Author: RUPA KRISHNA | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[Documents] DCM

Description: Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for the use of VHDL-based cases. This document for personal study and summary
Platform: | Size: 163840 | Author: 张潘睿 | Hits:

[VHDL-FPGA-Verilog] multiplier_booths

Description: a verilog code for booths multiplier has been uploaded, simple architecture.
Platform: | Size: 1024 | Author: JK | Hits:

[VHDL-FPGA-Verilog] floating_multi

Description: Floating point multiplier
Platform: | Size: 1781760 | Author: Alam | Hits:

[OS program] Multiplier

Description: 基于VHDL语言，实现串并乘法器设计主程序-Based on the VHDL language, to achieve the main program string and Multiplier Design
Platform: | Size: 3072 | Author: 小涛 | Hits:

[Other] mult

Description: floating point multiplier
Platform: | Size: 2048 | Author: prashanthi | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: verilog program for 8-bit multiplier
Platform: | Size: 216064 | Author: Arjun | Hits:
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