Search - multiplier

[VHDL-FPGA-Verilog] ade

Description: 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] mult_addtree

Description: 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] cmultip

Description: 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
Platform: | Size: 1024 | Author: xiaobai | Hits:

Description: RobustPCA 是最近提出的一种非常新的图像矩阵分解算法，该算法具有对噪声不敏感、能处理高维图像数据的特点。这是论文作者提供的 MATLAB 实现代码。-Oct 2009 This matlab code implements the augmented Lagrange multiplier method for Robust PCA.
Platform: | Size: 770048 | Author: bsmsht | Hits:

[matlab] lamao

Description: 用拉格朗日乘子法求解约束最优化问题，很好的实例程序。-Lagrange multiplier method for solving constrained optimization problems, very good example programs.
Platform: | Size: 164864 | Author: 辉少 | Hits:

[VHDL-FPGA-Verilog] mutiplier_4bits

Description: 通过移位相加，实现两个数的相乘。通过一个内部寄存器存储得到的积。--- it multiplies a 5_bit multiplicand by a 5_bit multiplier to give -- an 8_bit product -- -- aim: to master the method of mutiplier "shift and add to realize the mutiplier" --
Platform: | Size: 1024 | Author: lw | Hits:

[VHDL-FPGA-Verilog] 8by8multiplier

Description: Verilog HDL for 8*8 multiplier-Verilog HDL for 8*8 multiplier..
Platform: | Size: 49152 | Author: VINOD | Hits:

[VHDL-FPGA-Verilog] CSDmultiplier

Description: Code for CSD Multiplier
Platform: | Size: 1024 | Author: yuvi | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: Multiplier analysis presentation which includes area, power and delay
Platform: | Size: 263168 | Author: p2p_123 | Hits:

[VHDL-FPGA-Verilog] multiplier_csa

Description: 8 bit Multiplier, CSA type
Platform: | Size: 1024 | Author: kk | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: 使用三种不同结构（加法树、查找表、Booth算法）实现的乘法器，带有测试文件。-Use of three different structures (addition tree, look-up table, Booth algorithm) to achieve the multiplier, with testbench files.
Platform: | Size: 4096 | Author: 马昭鑫 | Hits:

[Special Effects] inexact_alm_rpca

Description: RPCA (Robust Principal Component Analysis)是目前用于矩阵填充、图像去噪的最有效的优化方法。目前最有效的算法是ALM（Augmented Lagrange Multiplier）。ALM分为Exact ALM和Inexact ALM。该代码是Inexact ALM，收敛速度比Exact ALM快！-RPCA (Robust Principal Component Analysis) is used for matrix filling, image denoising. It is currently the most effective optimization method. Currently the most effective method is ALM (Augmented Lagrange Multiplier). There re 2 kinds of ALM: Exact ALM and Inexact ALM. The code is Inexact ALM, faster convergence speed than the Exact ALM!
Platform: | Size: 380928 | Author: Bingmiao Huang | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 采用移位相加方法设计的串行乘法器，具有握手信号（输入启动信号，输出完成信号），采用状态机方法设计的源代码。-A serial multiplier with a handshake signals (input start signal, the output completion signal), designed by adder and shifter using a state machine.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] 8multipler

Description: 用VHDL实现8位移位相加乘法器，从被乘数的最低位开始，若为1，则乘数左移后与上次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。-VHDL 8-bit shift by adding the multiplier to achieve, starting from the lowest multiplicand, if 1, then left after the multiplier and add the last if 0, left after adding all 0, until the highest bit multiplicand.
Platform: | Size: 1024 | Author: ruanxioafei | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: paralel multiplier in verilog
Platform: | Size: 1024 | Author: mohammad | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: vhdl code multiplier
Platform: | Size: 1024 | Author: Nikhil | Hits:

[Algorithm] Ponytail

Description: How to Simulate A Ponytail - The Sample App This is a very simple Lagrange Multiplier constrained dynamics simulator to accompany my articles and lectures on How to Simulate a Ponytail. For more information, see http://chrishecker.com/How_to_Simulate_a_Ponytail The code should be relatively portable. There s a glut interface that has probably rotted but shouldn t be too hard to get working. The Ax=b matrix solver is from http://www.netlib.org/c/sge.shar, and I think it s public domain because it s a US Government contribution. If you ve got Visual C++ 6.0 installed and have an OpenGL library, you can compile and execute it. -How to Simulate A Ponytail - The Sample App This is a very simple Lagrange Multiplier constrained dynamics simulator to accompany my articles and lectures on How to Simulate a Ponytail. For more information, see http://chrishecker.com/How_to_Simulate_a_Ponytail The code should be relatively portable. There s a glut interface that has probably rotted but shouldn t be too hard to get working. The Ax=b matrix solver is from http://www.netlib.org/c/sge.shar, and I think it s public domain because it s a US Government contribution. If you ve got Visual C++ 6.0 installed and have an OpenGL library, you can compile and execute it.
Platform: | Size: 168960 | Author: woojin | Hits:

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[VHDL-FPGA-Verilog] ade

[VHDL-FPGA-Verilog] mult_addtree

[VHDL-FPGA-Verilog] cmultip

[Special Effects] rpca

[matlab] lamao

[VHDL-FPGA-Verilog] mutiplier_4bits

[VHDL-FPGA-Verilog] 8by8multiplier

[VHDL-FPGA-Verilog] CSDmultiplier

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] multiplier_csa

[VHDL-FPGA-Verilog] Multiplier

[Special Effects] inexact_alm_rpca

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] 8multipler

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] multiplier

[Algorithm] Ponytail

[VHDL-FPGA-Verilog] Booth_Multiplier_8bit_Radix_4_With_12bit_Adder_Ko

[VHDL-FPGA-Verilog] array_multiplier

[VHDL-FPGA-Verilog] multiplier

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