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[Other] multiplier

Description: .v files for multiplier
Platform: | Size: 15360 | Author: Ifrah | Hits:

[VHDL-FPGA-Verilog] fpu_v19

Description: Floating Point Multiplier in VHDL
Platform: | Size: 343040 | Author: shanmuga raja | Hits:

[Other] Multiplier

Description: A multiplier unit in VHDL
Platform: | Size: 1024 | Author: Sonali | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: this a multiplier in VHDL-this is a multiplier in VHDL
Platform: | Size: 1024 | Author: ali | Hits:

[VHDL-FPGA-Verilog] 16bit_mult

Description: 16位的无符号数乘法器，自己写的，经得起验证，注释很详细-16-bit unsigned multiplier, its own written
Platform: | Size: 323584 | Author: 郭富民 | Hits:

[VHDL-FPGA-Verilog] dsa_code

Description: Verilog code for synthesis of 8-bit booth multiplier
Platform: | Size: 4096 | Author: tanish | Hits:

[Software Engineering] doublemult

Description: 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确并对FPGA 实现的时序结果进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm for BOO TH generate part of the plot, with a mixed array and a tree structure to achieve the sum of the partial product, while also using a fast rounding algorithm to improve the performance of multipliers. The design of the multiplier is divided into four lines, carried out a simulation using FPGA verification result is correct and FPGA timing to achieve the results analyzed.
Platform: | Size: 209920 | Author: terry | Hits:

[Embeded-SCM Develop] wallacetreemultiplier

Description: wallace tree multiplier n bit c program
Platform: | Size: 8192 | Author: sneha | Hits:

[Embeded-SCM Develop] wallace_tree_multiplier_part1

Description: wallace tree multiplier
Platform: | Size: 181248 | Author: sneha | Hits:

[VHDL-FPGA-Verilog] multiplier

Description:
Platform: | Size: 15360 | Author: lurker | Hits:

[Books] VHDL

Description: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. -A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
Platform: | Size: 7168 | Author: Michael Lee | Hits:

[VHDL-FPGA-Verilog] GAFF

Description: 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
Platform: | Size: 2048 | Author: dayu1994 | Hits:

[VHDL-FPGA-Verilog] matrix3x3

Description: 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
Platform: | Size: 4096 | Author: wjlsomeone | Hits:

[Other] multiplier8x8

Description: 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
Platform: | Size: 2048 | Author: superbear | Hits:

[Industry research] ADSP-21262

Description: High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)-High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data (SIMD) computational architecture— two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital applications interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)
Platform: | Size: 507904 | Author: ak | Hits:

[VHDL-FPGA-Verilog] multiplier.tar

Description: 用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过-Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass
Platform: | Size: 2048 | Author: 胡恩 | Hits:

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[Other] multiplier

[VHDL-FPGA-Verilog] fpu_v19

[Other] Multiplier

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] 16bit_mult

[VHDL-FPGA-Verilog] dsa_code

[Software Engineering] doublemult

[Embeded-SCM Develop] wallacetreemultiplier

[Embeded-SCM Develop] wallace_tree_multiplier_part1

[VHDL-FPGA-Verilog] multiplier

[Books] VHDL

[VHDL-FPGA-Verilog] GAFF

[VHDL-FPGA-Verilog] matrix3x3

[Other] multiplier8x8

[Industry research] ADSP-21262

[VHDL-FPGA-Verilog] multiplier.tar

[VHDL-FPGA-Verilog] multiplier

[MiddleWare] multiplier

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] CourseDesign

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