Search - multiplier

[VHDL-FPGA-Verilog] Multiplier

Description: verilog implementation of the 32bit multiplier
Platform: | Size: 1024 | Author: ramtin | Hits:

[Windows Develop] multiplier-

Description: 模拟计算机中乘法器的运行过程，用到了Booth算法-The operation of the computer simulation of the multiplier process, use of the Booth algorithm
Platform: | Size: 3072 | Author: 谢伟 | Hits:

[VHDL-FPGA-Verilog] 8-by-8-Multiplier

Description: 8x8 bit multiplication verilog code
Platform: | Size: 50176 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 4 bit ordinary multiplier
Platform: | Size: 4096 | Author: arsha | Hits:

[VHDL-FPGA-Verilog] MULTIPLIER

Description: A TWO BYTE MULTIPLIER SYNTHESIABLE
Platform: | Size: 1833984 | Author: gopala | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: A VHDL program for multiplier, which has been used as a main source for a fir filter
Platform: | Size: 70656 | Author: siva | Hits:

Description: 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operations, but also to complete the sub-word parallel operation mode, that is, four 16bit* 16bit multiplication operation.
Platform: | Size: 99328 | Author: 余娅 | Hits:

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

Description: ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project we compare the working of the three multiplier by implementing each of them separately in FIR filter.
Platform: | Size: 379904 | Author: phitoan | Hits:

[Other] multiplier

Description: 增广乘子法，优化算法程序，采用Fortran语言编写-Augmented multiplier method, optimization procedures, using Fortran language
Platform: | Size: 1024 | Author: 张克 | Hits:

[VHDL-FPGA-Verilog] mult

Description: 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
Platform: | Size: 2048 | Author: yolin | Hits:

[VHDL-FPGA-Verilog] 4-multiplier-_vhdl

Description: 4 bit multiplier which can be use for making projects......can also be stimulated on spartan kits
Platform: | Size: 1024 | Author: jj | Hits:

[matlab] Multiplier-method

Description: 乘子法求解约束方程老师编的一段程序注释非常详细-Multiplier method to solve a series of constraint equations teachers very detailed program notes
Platform: | Size: 1024 | Author: mxf | Hits:

[VHDL-FPGA-Verilog] MULTIPLIER

Description: 基于VHDL硬件描述语言设计的乘法器，位数可以修改-VHDL hardware description language based on the design of the multiplier, the median can be modified
Platform: | Size: 1024 | Author: 橡树 | Hits:

[VHDL-FPGA-Verilog] multiplier_ip

Description: 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
Platform: | Size: 2784256 | Author: chenlan | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: VHDL语言设计的乘法器，经过试验箱测试通过，用试验箱的8个拨码开关输入数字，按键按下输出结果。-VHDL language design of multiplier, after chamber test, with the chamber of the 8 DIP switch input numbers, key press output.
Platform: | Size: 2048 | Author: 李志强 | Hits:

[Other] lagrange-multiplier

Description: Larange Multipliers-Larange Multipliers...........
Platform: | Size: 107520 | Author: moon | Hits:

[VHDL-FPGA-Verilog] VHDL-based-8-bit-multiplier

Description: 基于VHDL的8位乘法器运算程序，运用移位迭代法运算得出-VHDL-based 8-bit multiplier operation procedures, the use of shift operations derived iterative method
Platform: | Size: 3072 | Author: 周益驰 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 压缩的乘法器。是基于VERILOG 语言实现的，有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
Platform: | Size: 1024 | Author: hydan yi | Hits:

[VHDL-FPGA-Verilog] carry-save-multiplier-Verilog-code

Description: 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code
Platform: | Size: 1024 | Author: zhang chunhui | Hits:

[VHDL-FPGA-Verilog] lowpower-multiplier

Description: 32位无符号低功耗的乘法器,经过10000次测试,用smic.13工艺,DC综合后,延时为8ns,功耗仅为635uw.-it is an unsigned 32bit multiplier.100000 benchmarks have been tested and all of them passed. With smic 0.13um process library, after disign complier analysis, the clock period is 8ns,and the power consumption is only 635uw
Platform: | Size: 3072 | Author: | Hits:

« 1 2 ... 4 5 6 7 8 910 11 12 13 14 ... 50 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] Multiplier

[Windows Develop] multiplier-

[VHDL-FPGA-Verilog] 8-by-8-Multiplier

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] MULTIPLIER

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

[Other] multiplier

[VHDL-FPGA-Verilog] mult

[VHDL-FPGA-Verilog] 4-multiplier-_vhdl

[matlab] Multiplier-method

[VHDL-FPGA-Verilog] MULTIPLIER

[VHDL-FPGA-Verilog] multiplier_ip

[VHDL-FPGA-Verilog] Multiplier

[Other] lagrange-multiplier

[VHDL-FPGA-Verilog] VHDL-based-8-bit-multiplier

[VHDL-FPGA-Verilog] multiplier

[VHDL-FPGA-Verilog] carry-save-multiplier-Verilog-code

[VHDL-FPGA-Verilog] lowpower-multiplier

CodeBus www.codebus.net