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[VHDL-FPGA-Verilog] 8bit-Shift-and-Adder--multiplier

Description: 8位乘法器，经移位相加算法来实现的，用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
Platform: | Size: 584704 | Author: Aaran | Hits:

[Software Engineering] 4-bit-multiplier

Description: 4 bit multiplier program using shift and multiply
Platform: | Size: 2048 | Author: karthick | Hits:

[VHDL-FPGA-Verilog] mult

Description: 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete the functional design of the multiplier, and Modelsim for simulation by verification.
Platform: | Size: 4096 | Author: xiu | Hits:

[VHDL-FPGA-Verilog] Small-multiplier

Description: 小型倍频器，简单的介绍了如何用verilog写倍频电路》-Small multiplier
Platform: | Size: 1323008 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] VHDL-test-codeBooth-multiplier

Description: VHDL实验代码：Booth乘法器，是一个基于VHDL语言开发的程序，非常的实用-VHDL test code: Booth multiplier, is a VHDL-based language development program, a very practical
Platform: | Size: 1024 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] 32_bit_complex_multiplier

Description: 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
Platform: | Size: 8192 | Author: wilson | Hits:

[VHDL-FPGA-Verilog] The-design-of-multiplier

Description: 国防科技大学的一篇高速乘法器算法的论文,应用于FPGA-National Defense University in a high-speed multiplier algorithm paper, used in FPGA
Platform: | Size: 32768 | Author: zhaozhijie | Hits:

[VHDL-FPGA-Verilog] CCMU

Description: 代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少-Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less
Platform: | Size: 2048 | Author: 方波 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 几种verilog乘法器的代码，用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
Platform: | Size: 10240 | Author: 马力维 | Hits:

[VHDL-FPGA-Verilog] booth

Description: radix 2 booth multiplier verilog code
Platform: | Size: 1024 | Author: Hanumantha Reddy | Hits:

[VHDL-FPGA-Verilog] VHDL-Multiplier

Description: 资料是EDA的一个课程设计，基于VHDL实现的乘法器，包含论文，欢迎下载-EDA data is a course designed to achieve a multiplier based on VHDL, including paper, please download
Platform: | Size: 287744 | Author: wangwenhao | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 参数可配置的sequential 乘法器和booth 乘法器-verilog source code with configurable parameters for sequential multiplier and booth multiplier
Platform: | Size: 2048 | Author: shuanghx | Hits:

[VHDL-FPGA-Verilog] array-multiplier

Description: source code for array multiplier
Platform: | Size: 1024 | Author: pavan vinayak | Hits:

[VHDL-FPGA-Verilog] 67719585-Booth-Multiplier-Vhdl-Code

Description: vhdl code for booth multiplier-vhdl code for booth multiplier...........................
Platform: | Size: 10240 | Author: satya | Hits:

[matlab] multiplier-method

Description: 用乘子法求解约束优化问题。使用实例进行说明。程序给出。-With the multiplier method to solve the constrained optimization problem. Program are given.
Platform: | Size: 3072 | Author: selina | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 32位乘以32位乘法器，由datapath 和控制中心组成，输出64位结果-32bits by 32 bits multiplier
Platform: | Size: 2048 | Author: luna | Hits:

[VHDL-FPGA-Verilog] 8-8-array-multiplier

Description: a multiplier structural code
Platform: | Size: 3072 | Author: hj | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Multiplier-in-Verilog

Description: Floating Point Multiplier in Verilog
Platform: | Size: 64512 | Author: Khalid Nawaz Khan | Hits:

[VHDL-FPGA-Verilog] 4-x-4-on-time-multiplier--table

Description: 4×4 查找表乘法器 vhdl 语言描述-4 x 4 on time-multiplier look-up table VHDL language describe
Platform: | Size: 252928 | Author: 郭少华 | Hits:

[VHDL-FPGA-Verilog] 16-parallel-multiplier

Description: 简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
Platform: | Size: 2048 | Author: 陈俊辉 | Hits:
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