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[VHDL-FPGA-Verilog] mult16

Description: 基于wallance树的16位乘法器，程序是用verilog写的，经测试好用，对初学者有很大的帮助-16-bit multiplier, based on wallance tree program is written with verilog test handy for beginners great help
Platform: | Size: 2048 | Author: 天空 | Hits:

[MiddleWare] multiplier_interface

Description: verilog 写的工程，是个基于流水线的乘法器-verilog write the works, is based on a pipelined multiplier
Platform: | Size: 3072 | Author: wns | Hits:

[Compress-Decompress algrithms] RDTLT

Description: 基于Lossy-to-Lossless Image Compression Based on Reversible Integer TDLT/KLT的压缩算法的matlab实现，在增加ROI编码模块，算法详细可以查看论文《Lossy-to-lossless image compression based on multiplier-less reversible integer time domain lapped transform》。程序由main.m函数开始运行，输入参数有3个，分别是图像的文件名(该文件夹内的.raw文件)，图像的宽和高。-Lossy-to-Lossless Image Compression Based on Reversible the Integer TDLT/KLT compression algorithm matlab realize increased ROI coding module, the algorithm in detail you can view papers " Lossy-to-lossless image compression based on multiplier-less reversible integer time domain lapped transform " . Program run by the main.m function, three input parameters, the image file name (the file folder. Raw file), the width and height of the image.
Platform: | Size: 1179648 | Author: huangdacheng | Hits:

[Other] mux16

Description: 一个流水线的16X16的乘法器，经过验证，很好的代码-16X16 multiplier, a pipeline proven good code
Platform: | Size: 1024 | Author: 李军 | Hits:

[matlab] RateDF

Description: 信息率失真函数的迭代计算 信息率失真函数的迭代计算，迭代精度取为10^(-7) 在信源的输入概率分布Pa和失真矩阵d已知的条件下求出信息率失真函数 函数说明： [Pba,Rmin,Dmax,Smax]=RateDF(Pa,d,S) 为信息率失真函数 变量说明： Pa：信源的输入概率矩阵，d：失真矩阵，S：拉氏乘子 Pba：最佳正向转移概率矩阵， Smax：最大拉氏乘子 Rmin：最小信息率，Dmax：允许的最大失真度 -Information rate distortion function iteration rate-distortion function iteration, iteration accuracy 10 ^ (-7) source input probability distribution of Pa and distortion matrix d known conditions obtained information rate distortion function Function Description: [Pba, Rmin, Dmax, Smax] = RateDF (Pa, d, S) for the information rate distortion function Variable Description: Pa: source input probability matrix, d: Distortion matrix, S: Lagrangian multiplier Pba: Best forward transition probability matrix, Smax: maximum Lagrangian multiplier Rmin: Minimum information rate, Dmax: Allow the maximum distortion
Platform: | Size: 2048 | Author: 龙哥 | Hits:

[VHDL-FPGA-Verilog] wallace

Description: wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of both dct and dwrt applications-wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of both dct and dwrt applications
Platform: | Size: 3072 | Author: ganesh | Hits:

[Other] lagrange

Description: 求解约束最优化问题，一种途径是在可行域内寻找使目标函数值下降的迭代点列，但是这类方法对于带非线性约束的最优化问题求解效果一般都不理想。因此我们利用另一种途径，即利用问题的目标函数和约束函数构造新的目标函数——罚函数，把约束最优化问题转化为相应的罚函数的无约束最优化问题来求解实际问题。-lagrange constraint multiplier method for the minimum
Platform: | Size: 2048 | Author: 王喜 | Hits:

[Algorithm] limit

Description: 极值法是一种重要的数学思想和分析方法。化学上所谓“极值法”就是对数据不足而感到无从下手的计算或混合物组成判断的题目，采用极端假设（即为某一成分或者为恰好完全反应）的方法以确定混合体系中各物质的名称、质量分数、体积分数，这样使一些抽象的复杂问题具体化、简单化，可达到事半功倍之效果。 -The extremum law is an important mathematical thinking and analytical methods. Chemical on the so-called " extreme value method is the lack of data was impossible to start the calculation or the mixture of the judgment subject to extreme assumptions (ie a particular ingredient or exactly complete reaction) method to determine the material mixed system Name, mass fraction, volume fraction, so that some the abstract complex issues concrete, simplistic, can achieve a multiplier effect.
Platform: | Size: 1024 | Author: 王喜 | Hits:

[VHDL-FPGA-Verilog] Chapter4

Description: Chapter4文件夹： （1）实验1：编码器实验，完整的设计工程文件在CODER文件夹下 （2）实验2：译码器实验，完整的设计工程文件在DECODER7文件夹下 （3）实验3：加法器实验，完整的设计工程文件在ADDER和ALU文件夹下 （4）实验4：乘法器实验，完整的设计工程文件在4BITMULT文件夹下 （5）实验5：寄存器实验，完整的设计工程文件在SHIFT8R和SHIFT8文件夹下 （6）实验6：计数器实验，完整的设计工程文件在COUNT10文件夹下 （7）实验7：分频器实验，完整的设计工程文件在ODD_DEV_F文件夹下 （8）实验8：存储器实验，完整的设计工程文件在RAM文件夹下-Chapter4 folder: (1) Experiment 1: encoder experiment, the complete design engineering documents in the the CODER folder (2) Experiment 2: decoder experiments, complete design engineering documents under the folder DECODER7 (3) Experiment 3 : adder experiment, complete design engineering documents in the the ADDER and ALU folder (4) Experiment 4: Multiplier experiment, a complete design engineering documents in 4BITMULT folder (5) Experiment 5: register experiment complete design engineering file under the SHIFT8R and SHIFT8 folder (6) Experiment 6: counter experiment, a complete design the project file the COUNT10 folder (7) Experiment 7: divider experimental design the project file the ODD_DEV_F folder (8 ) Experiment 8: memory experiments, complete design project files in the the RAM file folder under
Platform: | Size: 1654784 | Author: boyzone | Hits:

[VHDL-FPGA-Verilog] wu1_selfcheck_beh_0

Description: 32位的乘法器，能在ISE软件中进行仿真。能看到仿真效果。-32-bit multiplier, the ISE software simulation. Can see the simulation results.
Platform: | Size: 2048 | Author: 吴凤妹 | Hits:

[VHDL-FPGA-Verilog] di3

Description: IP核和乘法运算模块分别有两个输入端口a、b和clk时钟脉冲信号及一个输出端口p，用例化语句将这两个模块合成一个乘法器后就生成了由两个输入端口a、b和clk时钟脉冲信号及两个输出端口p1、p2组成。-IP cores and multiplication module respectively, the two input ports of a, b, and clk clock signal and an output port p, these two modules with the instantiation statements Synthesis of a multiplier by two input ports, a, b are generated after and the the CLK clock pulse signals and two output ports p1, p2.
Platform: | Size: 1024 | Author: 吴凤妹 | Hits:

[Other] ARM9.pdf

Description: 以ARM9E-S为例介绍ARM9处理器的主要结构及其特点。ARM9E-S的结构如图4所示。其主要特点如下： (1)32bit定点RISC处理器，改进型ARM／Thumb代码交织，增强性乘法器-ARM9E-S, for example the main structure and its characteristics on ARM9 processor. ARM9E-S structure is shown in Figure 4. Its main features are as follows: (1) 32bit the sentinel RISC processor, improved ARM/Thumb code intertwined enhance sexual multiplier ...
Platform: | Size: 4930560 | Author: zhaoxinyue | Hits:

[Other] Constrained-optimization-problems

Description: 约束优化问题，包含 用Rosen梯度投影法求解约束多维函数的极值 用外点罚函数法求解线性等式约束多维函数的极值 用外点罚函数法求解一般等式约束多维函数的极值 用内点罚函数法求解约束多维函数的极值 用混合罚函数法求解约束多维函数的极值 用混合罚函数加速法求解约束多维函数的极值 用乘子法求解约束多维函数的极值 用坐标轮换法求解约束多维函数的极值 用复合形法求解约束多维函数的极值 -Constrained optimization problems containing Rosen gradient projection method for solving constrained multi-dimensional functions the extremal with outside point penalty function method for solving linear equality constraints multidimensional function extreme outside point penalty function method for solving general the equality constraints multidimensional function extremum interior point penalty function method for solving constrained multidimensional function extremum with mixed penalty function method for solving constrained multidimensional function extremum with mixed penalty function accelerated method for solving constrained multidimensional function extremum multiplier method for solving constrained multidimensional function extremum with coordinate rotation method for solving constrained multi-dimensional function the extremal complex method for solving constrained multidimensional function extremum
Platform: | Size: 4096 | Author: 张然 | Hits:

[VC/MFC] High-quality-C-P-P-Programming-Guide

Description: 书中用对比的方式展示了良好的编程习惯、高质量的代码的重要性，结合作者的实践经验，是初学者必备，事半功倍提高编程水平的好书-Demonstrate good programming practice book with way of contrast, the importance of high-quality code, combined with the author' s practical experience, beginners must multiplier to improve the level of programming books
Platform: | Size: 605184 | Author: 老大 | Hits:

[matlab] SALSA_v2.0

Description: 应用交替方向乘子法来求解L1正则化问题、BP问题、LASSO问题的一种算法，-Application alternating direction multiplier method to solve L1 regularization problem, BP issue LASSO problem an algorithm
Platform: | Size: 241664 | Author: yangzhenzhen | Hits:

[matlab] YALL1-v1.4

Description: 用交替方向乘子法来求解L1正则化问题、BP问题、BPDN问题的一种算法-An algorithm for solving the L1 regularized problem, BP issue BPDN problem with alternating direction multiplier method
Platform: | Size: 5852160 | Author: yangzhenzhen | Hits:

[matlab] PHR

Description: 本算法是乘子法MATLAB的通用程序，只要输入相应的参数即可运行-This algorithm is a the multiplier method MATLAB common procedures as long as the input parameters to run
Platform: | Size: 2048 | Author: 易风 | Hits:

[VHDL-FPGA-Verilog] develop_frame_find

Description: 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower than the previous algorithm, but very practical.
Platform: | Size: 320512 | Author: | Hits:

[Other] mux16

Description: 乘法器，verilog语言实现，16位*16位，位数可调，改动相应程序即可。-Multiplier, verilog language to achieve, 16* 16 digit adjustable changes corresponding program can.
Platform: | Size: 1024 | Author: 胡峰 | Hits:

[SCM] mini80E

Description: mini80E开发板资料，有开发板电路图和STC89C51单片机程序，源码丰富，让你学习51单片机事半功倍-the mini80E development board, the development plate circuit diagram and STC89C51 of SCM process, rich source, you learn 51 microcontroller multiplier
Platform: | Size: 14344192 | Author: 留侯 | Hits:
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