- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2012-11-26
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- 0 Times
- Uploaded by:
- 吴凤妹
Description: IP cores and multiplication module respectively, the two input ports of a, b, and clk clock signal and an output port p, these two modules with the instantiation statements Synthesis of a multiplier by two input ports, a, b are generated after and the the CLK clock pulse signals and two output ports p1, p2.
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