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[VHDL-FPGA-Verilog] booth

Description: 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
Platform: | Size: 1024 | Author: gyj | Hits:

[MPI] Multiplier

Description: 用VHDL语言仿真乘法器设计。能够实现一般乘法运算。-Multiplier using VHDL language design simulation. Multiplication can be achieved in general.
Platform: | Size: 84992 | Author: 吴伟 | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial
Platform: | Size: 279552 | Author: liuning | Hits:

[VHDL-FPGA-Verilog] multiplier_8_bit

Description: This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.
Platform: | Size: 3072 | Author: KC.Park | Hits:

[VHDL-FPGA-Verilog] WallaceTreeMultiplier

Description: Wallace Tree Multiplier in VHDL for 4bit operation fully using structural language
Platform: | Size: 2354176 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] 8bit_adder_AND_4x4_Multiplier

Description: 位加法器的verilog程序与4×4 乘法器的verilog描述-Verilog-bit adder of the procedures and 4 × 4 multiplier verilog description! ! !
Platform: | Size: 1024 | Author: mhb | Hits:

[Other] mul

Description: 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to the median minus 1, adder operand median accuracy of the 2-fold, and the gate count required operand equal to the square. 8-bit multiplier, therefore the need for 7 and 15 adder 64 and the door
Platform: | Size: 1024 | Author: 肖毅 | Hits:

[Embeded-SCM Develop] BoothMultiplier4

Description: Radix 4 Booth Multiplier
Platform: | Size: 201728 | Author: photo26 | Hits:

[VHDL-FPGA-Verilog] Galois_field_multiplier_verilog_design

Description: 伽罗华域GF（q）乘法器verilog设计.rar-Galois field GF (q) multiplier verilog design.rar
Platform: | Size: 2048 | Author: 海天之洲 | Hits:

[Other] MUL

Description: 8-bit modified Booth s algorithm multiplier
Platform: | Size: 80896 | Author: calvin | Hits:

[Embeded-SCM Develop] 16_bit

Description: 采用boot算法的16位乘法器,速度较快，可以试下哈-Boot algorithm using 16-bit multiplier, faster, you can try under the Kazakhstan
Platform: | Size: 5120 | Author: aaa | Hits:

[VHDL-FPGA-Verilog] nxn_multiplier

Description: Verilog module for hardware N x N multiplier using generate keyword.
Platform: | Size: 1024 | Author: ifusmell | Hits:

[VHDL-FPGA-Verilog] mux4

Description: 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic description of
Platform: | Size: 203776 | Author: 望天 | Hits:

[Embeded-SCM Develop] test_bench

Description: test bench for booth multiplier
Platform: | Size: 1024 | Author: judy | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
Platform: | Size: 1024 | Author: avi | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
Platform: | Size: 113664 | Author: 刘佳扬 | Hits:

[VHDL-FPGA-Verilog] qfq

Description: 移位相加乘法器设计。附有工程实例及ppt说明。-Add multiplier design shift. Ppt with example and description.
Platform: | Size: 1726464 | Author: fddib | Hits:

[Software Engineering] FPGA

Description: 基于FPGA数字乘法器的设计：数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA 的数字乘法器．分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processing in the most extensive one of the implementation of components, the paper design of the three types of FPGA-based digital multiplier. Shift sum are noise multiplication, adder tree multiplier and the sum of a displacement hybrid adder tree multiplier noise. Through the simulation of three options to building a comprehensive comparison of the speed and size that the multiplier is one of the best hybrid design
Platform: | Size: 147456 | Author: 南才北往 | Hits:

[Windows Develop] BaughWooleyMultiplier

Description: Baugh Wooley Multiplier
Platform: | Size: 1024 | Author: Harsha | Hits:

[Windows Develop] mult4x4_1

Description: There are 4 bit by 4 bit multiplier to give 8 bit product
Platform: | Size: 1024 | Author: abbc | Hits:
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