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Description: 8 bit multiplier with pipeline design, mainly for studying and learning purpose
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Size: 1024 |
Author: q |
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Description: booth 乘法器 不同于传统的算法实现-booth multiplier is different from the traditional algorithm
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Size: 1024 |
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Description: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
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Size: 1024 |
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Description: 在gf(2^13)中,固定因子乘法器(基于自然基,0-128)-In gf (2 ^ 13), the fixed-factor multiplier (based on the natural base ,0-128)
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Size: 47104 |
Author: 张凯斌 |
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Description: 高效结构的多输入浮点乘法器在FPGA上的实现-Efficient structure of multi-input floating-point multiplier in FPGA Implementation
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Size: 140288 |
Author: stormy |
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Description: VHDL实现倍频--偶数倍 分频电路
--分频倍数=2(n+1)-VHDL realize many times frequency multiplier circuit dual frequency multiplier = 2 (n+ 1)
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Size: 145408 |
Author: 杨守望 |
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Description: 八位乘法器VHDL语言实现。使用的工具的ISE7.1,实现八乘八的位相乘。-8 Multiplier VHDL language. Tools used ISE7.1, realize eight by eight-bit multiplication.
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Size: 2048 |
Author: 周东永 |
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Description: 脉动乘法器:一个GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier
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Size: 2560000 |
Author: chenyi |
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Description: 8*8乘法器及其测试:采用booth编码的乘法器:1. ultipler_quick_add_4
即4位的并行全加器,在这里主要起了两个作用:第一个是在求部分积单元时,当编码为3x时用来输出部分积;另外一个是在将部分积加起来时,求3到6位时所用到。
2. ultiplier_quick_add_5
即5位的并行全加器,这里用来分别计算积的7到11位和12到16位。
3. ultiplier_unit_4
这个模块是用来实现部分积的,每一个模块实现一个部分积的4位,因此一个部分积需要4个这个模块来实现。总共需要12个这样的模块。
4.Multiplier_full_add
这是一位的全加器,在实现部分积相加的时候,通过全加器的阵列来实现的。
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Size: 9216 |
Author: chenyi |
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Description: 16*16有符号乘法器的
编码方式:Booth编码,
拓扑结构:简单阵列
加法器:Ripple Carry Adder-16* 16 multiplier symbols have the
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Size: 30720 |
Author: chenyi |
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Description: 移位相加8位硬件乘法器电路设计
乘法器是数字系统中的基本逻辑器件,在很多应用中都会出现如各种滤波器的设计、矩阵的运算等。本实验设计一个通用的8位乘法器。-Shift combined 8-bit hardware multiplier multiplier circuit design is a digital system in the basic logic devices, in many applications will emerge, and such a variety of filter design, such as matrix calculations. The experimental design of a generic 8-bit multiplier.
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Size: 5120 |
Author: jun |
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Description: 好用的浮点乘法器,可完成32位IEEE格式的浮点乘法,经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
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Size: 1024 |
Author: gulu |
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Description: 实现了VHDL乘法器,8位乘法操作的完成-VHDL realize a multiplier, an 8-bit multiplication operation completed
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Size: 3072 |
Author: zxzx |
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Description: 主題 :
Low power Modified Booth Multiplier
介紹 : 為了節省乘法器面積、加快速度等等,許多文獻根據乘法器中架構提出改進的方式,而其中在1951年,A. D. Booth教授提出了一種名為radix-2 Booth演算法,演算法原理是在LSB前一個位元補上“0”,再由LSB至MSB以每兩個位元為一個Group,而下一個Group的LSB會與上一個Group的MSB重疊(overlap),Group中的位元。
Booth編碼表進行編碼(Booth Encoding)後再產生部分乘積進而得到最後的結果。
Radix-2 Booth演算法在1961年由O. L. Macsorley教授改良後,提出了radix-4 Booth演算法(modified Booth algorithm),此演算法的差異為Group所涵括的位元由原先的2個位元變為3個位元。-Theme: Low power Modified Booth Multiplier Introduction: In order to save multiplier size, speed and so on, many papers multiplier in accordance with the framework to improve the way in which in 1951, AD Booth, a professor known as radix-2 Booth algorithm, algorithm theory is a bit LSB before the meeting on
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Size: 14336 |
Author: stanly |
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Description: ALTERA上DE2平台,verilog描述,无符号乘法器,在数码管显示结果。-ALTERA on DE2 platform, verilog description unsigned multiplier, the result will be displayed in the digital pipe.
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Size: 878592 |
Author: 徐朝凯 |
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Description: 基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source
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Size: 2048 |
Author: df |
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Description:
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Size: 1024 |
Author: dong |
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Description: 32位元2進位SIGNED乘法器32位元SIGNED乘法器-32-bit 2 binary SIGNED Multiplier Multiplier 32-bit SIGNED
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Size: 2048 |
Author: chen |
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Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
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Size: 4096 |
Author: lanty |
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Description: 54x54-bit Radix-4 Multiplier
based on Modified Booth Algorithm
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Size: 750592 |
Author: 汤江逊 |
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