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[VHDL-FPGA-Verilog] c17_GF_multiple

Description: 精通verilog HDL语言编程源码之3--伽罗华域乘法器设计-Proficient in language programming verilog HDL source of 3- Galois field multiplier design
Platform: | Size: 1024 | Author: 李平 | Hits:

[VHDL-FPGA-Verilog] 32-bit_multiplier_model

Description: 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
Platform: | Size: 2048 | Author: zhaohongliang | Hits:

[VHDL-FPGA-Verilog] cmult

Description: 复乘法器的FPGA实现， 希望对初学者有帮助 -Complex Multiplier FPGA to achieve, and they hope to help beginners
Platform: | Size: 1052672 | Author: shirley | Hits:

[VHDL-FPGA-Verilog] multi16

Description: verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
Platform: | Size: 7168 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] mult_piped_8x8

Description: 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
Platform: | Size: 1024 | Author: 江浩 | Hits:

[Crack Hack] mulf2m

Description: 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。-Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
Platform: | Size: 1024 | Author: 傅建新 | Hits:

[VHDL-FPGA-Verilog] multiply

Description: Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] GFmultiply

Description: Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[Other] mux8

Description: 定点八位乘法器的原理图设计，已通过功能仿真！-8 fixed-point multiplier schematic design, functional simulation has passed!
Platform: | Size: 412672 | Author: lxp | Hits:

[VHDL-FPGA-Verilog] Wallace

Description: 一个关于Wallace树乘法器的论文，当中展示了一种改进后的wallace树乘法器方案，相比原来占用晶体管更少，效率更高-Wallace tree multiplier on the papers, which show an improved wallace tree multiplier after the program, compared to the original transistors occupy less efficient
Platform: | Size: 106496 | Author: szx | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[Documents] code

Description: code for booths multiplier
Platform: | Size: 2048 | Author: sathish | Hits:

[Software Engineering] booth_multiplier

Description: Booth multiplier written in verilog
Platform: | Size: 1024 | Author: Udit | Hits:

[Books] 32bit

Description: model algorithm for 32 bit multiplier
Platform: | Size: 302080 | Author: damasqas | Hits:

[ELanguage] 32bit

Description: multiplier and divider verilog codes
Platform: | Size: 6144 | Author: damasqas | Hits:

[VHDL-FPGA-Verilog] freqm

Description: frequency multiplier
Platform: | Size: 83968 | Author: nattu | Hits:

[VHDL-FPGA-Verilog] FinalFPMultiplier

Description: Simple 32 bit Floating point Multiplier
Platform: | Size: 7372800 | Author: Rahul | Hits:

[VHDL-FPGA-Verilog] Boothsmul

Description: Booths Multiplier using Behavioral Model
Platform: | Size: 3903488 | Author: Rahul | Hits:

[VHDL-FPGA-Verilog] booth

Description: 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
Platform: | Size: 1024 | Author: lixiang | Hits:

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度， 由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:
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