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Description: 1．设计一个可供4名选手参加比赛的4路数字显示抢答器。他们的编号分别为“1”、“2”、“3”、“4”各用一个抢答按钮，编号与参赛者的号码一一对应。
2．抢答器具有数据锁存功能，并将锁存的数据用LED数码管显示出抢答成功者的号码。
3．抢答器对抢答选手动作的先后有很强的分辨能力，即使他们的动作仅相差几毫秒，也能分辨出抢答者的先后来。即不显示后动作的选手编号。
4．主持人具有手动控制开关，可以手动清零复位，为下一轮抢答做准备。
-1. To design a game for four players to participate in the 4-channel digital display Responder. Their numbers are " 1" , " 2" , " 3" , " 4" with one answer in each button, and number-one correspondence with the number of contestants. 2. Responder has a data latch function, and the data latch with LED digital tube show to answer in successful numbers. 3. Responder right answer in the action player has the ability to distinguish strong, even if their action is only a difference of a few milliseconds, but also be able to distinguish those who have to answer in his place. That is, not displayed, the action player numbers. 4. Moderators have the manual control switch, you can manually clear the reset for the next one to answer in preparation.
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Size: 221184 |
Author: 李晓翔 |
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Description: latch in FPGA-latch in FPGA
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Size: 2048 |
Author: ramesh |
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Description: Specifications
1. Top module name :SS (File name : SS.v)
2. Input pins: CLK, RESET, IN_VALID, INPUT [6:0]
- 2 -
3. Output pins: OUT_VALID, OUTPUT [6:0]
4. Synchronous active high RESET is used, and no latch design is allowed.
5. All input signals will be changed at negative edge of clock. IN_VALID is high
when INPUT [6:0] is valid.
6. OUT_VALID will be high when OUTPUT is valid, and test pattern will compare
your output signals to the correct answer.
7. The valid output sequence must be continuous without any interruption.
8. Input delay and output delay are 0.5*clock period.
9. After synthesis, check the “SS.area” and “SS.timing” in the folder “Report”.
The area report is valid only when the slack in the end of SS.timing is
non-negative.
10. All outputs are sampled at negative clock edge.
11. The clock period is 5 ns.
12. The output loading is 0.05.
Platform: |
Size: 3353600 |
Author: chen-che,wemg |
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Description: 一种8位锁存器，程序简单，为初学者提供，一种简单的数据锁存方式。-a kind of eight bits latch。
Platform: |
Size: 1024 |
Author: 杨金磊 |
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Description: Introduction for latch and flip-flop.-latch and flip-flop is describe in this word file.
Platform: |
Size: 166912 |
Author: anthonykang |
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Description: 扫描显示译码控制部分用一个频率1KHz的信号扫描一个多路选择器，实现对六位已经锁存的计数结果的扫描输出-Scan revealed a decoding control part of the signal with a frequency of 1KHz scan more than one MUX to achieve a count of six has been the results of the scan latch output
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Size: 1024 |
Author: 安安 |
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Description: 以Lattice 器伴为例,描述如何在Verilog中指定管脚属饪功能(OE,RESET,IO CELL寄存器,双向IO,Latch IO,管脚Pin number, synthesis属性,输出电气规格...),状态机的使用,及其它Verilog进阶功能-With Lattice devices for example, it describes how to specify the pin function in Verilog (OE, RESET, IO CELL register, bi-directional IO, Latch IO, assign Pin number, synthesis properties, the output electrical specifications ...), using State Machine, and other advanced features of Verilog.
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Size: 126976 |
Author: Tim |
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Description: 该文档提出了一种应用于开关电容流水线模数转换器的CMoS预运放一锁存比较
器．该比较器采用UMC混合／射频0．18肛m 1P6M P衬底双阱CMOS工艺设计，工作电压为
1．8 V．该比较器的灵敏度为0．215 mV，最大失调电压为12 mV，差分输入动态范围为1．8
V，分辨率为8位，在40 M的工作频率下，功耗仅为24．4 ttW．基于0．18 gm工艺的仿真结
果验证了比较器设计的有效性．-A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·-
verter WBS presented．The comparator WaS d髑igned under UMC Mixed．Mode／RF 0．18 btm 1P6M P．Sub Twin—
Well CMOS process and worked with 1．8V power supply．The sensitivity of the comparator was 0．215 mV，
the largest offset voltage was 12 mV，the differentiaI input range Was 1．8 V，the resolution was 8 bit and the
power dissipation Was only 24．4 gW at 40 MHz．HSPICE simulations of the comparator implemented in a 0．18
um technology demonstrate its effectiveness．
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Size: 361472 |
Author: 赵恒 |
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Description: 基于ROM的正弦波发生器的设计
一．实验目的
1. 学习VHDL的综合设计应用
2. 学习基于ROM的正弦波发生器的设计
二．实验内容
设计基于ROM的正弦波发生器，对其编译，仿真。
具体要求：
1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based sine wave generator design
1. Purpose of the experiment
1. VHDL Integrated Design and Application of Learning
2. Learning ROM-based sine wave generator design
2. Experimental content
ROM-based sine wave generator design, its compilation, simulation.
Specific requirements:
1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules
Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB.
3. The 50MHz input clock.
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Size: 17408 |
Author: 爱好 |
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Description: 从芯片中读出转化后的数据并锁存，再并行输出-Read from the chip data transformation and latch, and then parallel output
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Size: 1024 |
Author: wangyanke |
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Description: Ｄ锁存器ＶＨＤＬ语言描述。使能端有效时，Ｑ《＝Ｄ-D latch described in VHDL language. Enable effective end when, Q " = D
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Size: 2048 |
Author: yuer |
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Description: 动态显示的特点是将所有位数码管的段选线并联在一起，由位选线控制是哪一位数码管有效。这样一来，就没有必要每一位数码管配一个锁存器，从而大大地简化了硬件电路。选亮数码管采用动态扫描显示。所谓动态扫描显示即轮流向各位数码管送出字形码和相应的位选，利用发光管的余辉和人眼视觉暂留作用，使人的感觉好像各位数码管同时都在显示。动态显示的亮度比静态显示要差一些，所以在选择限流电阻时应略小于静态显示电路中的。
-Dynamic display features all the bits of digital control of segment-select line connected in parallel, from the bit selector control which a digital control effectively. Thus, it is not necessary with each of the digital control of a latch, thereby greatly simplifying the hardware circuit. Select the digital control using dynamic light scanning display. The so-called dynamic scan revealed that in turn send to you the digital control code and the corresponding bit font selection, use of LED in the afterglow and the human visual temporary stay in effect, make people feel like you are in the display while the digital control. Dynamic display of the brightness of some worse than a static display, so the choice should be slightly less than the current limiting resistor, a static display in the circuit.
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Size: 243712 |
Author: 小北 |
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Description: 4~20毫安传感器变送程序 采用msp430-2013
//P1.5：数据输出
//P1.4：移位脉冲
//P1.6：锁存输出
//P1.2/A1+ P1.3/A1- 为外部传感器差动信号输入端-4 to 20 mA sensor transmitter program using msp430-2013// P1.5: data output// P1.4: shift pulse// P1.6: Latch the output// P1.2/A1+ P1.3/A1-differential signal for the external sensor input
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Size: 28672 |
Author: 林立新 |
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Description: 74HC/HCT373
Octal D-type transparent latch
3-state-74HC/HCT373 Octal D-type transparent latch 3-state
Platform: |
Size: 51200 |
Author: lin |
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Description: 如何让51hei单片机学习板上的led灯点亮，一个很简单的程序，有详细的注释，适合刚入门的初学者学习锁存器的使用-How to light up 51hei microcontroller development board led light, a very simple procedure detailed notes, suitable for beginners to learn just started to latch
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Size: 6144 |
Author: agdsafsd |
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Description: 单片机开发中使用的移位锁存器，完整的仿真电路和测试C程序代码。-Microcontroller used in the development of shift latch, a complete simulation of the circuit and test C code.
Platform: |
Size: 86016 |
Author: xunan |
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Description: 运用51单片控制锁存器译码器等，完成一个简单的计算器系统-Control the use of 51 single latch decoder and so on, to complete a simple calculator system
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Size: 37888 |
Author: shuyashuo |
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Description:
* When including this file in the assembly program file, all I/O register
* names and I/O register bit names appearing in the data book can be used.
*
* The Register names are represented by their hexadecimal addresses.
*
* The Register Bit names are represented by their bit number (0-7).
*
* Please observe the difference in using the bit names with instructions
* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
* (skip if bit in register set/cleared). The following example illustrates
* this:
*
* in r16,PORTB read PORTB latch
* sbr r16,(1<<PB6)+(1<<PB5) set PB6 and PB5 (use masks, not bit#)
* out PORTB,r16 output to PORTB
*
* in r16,TIFR read the Timer Interrupt Flag Register
* sbrc r16,TOV0 test the overflow flag (use bit#)
* rjmp TOV0_is_set jump if set
* ... otherwise do something else-
* When including this file in the assembly program file, all I/O register
* names and I/O register bit names appearing in the data book can be used.
*
* The Register names are represented by their hexadecimal addresses.
*
* The Register Bit names are represented by their bit number (0-7).
*
* Please observe the difference in using the bit names with instructions
* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
* (skip if bit in register set/cleared). The following example illustrates
* this:
*
* in r16,PORTB read PORTB latch
* sbr r16,(1<<PB6)+(1<<PB5) set PB6 and PB5 (use masks, not bit#)
* out PORTB,r16 output to PORTB
*
* in r16,TIFR read the Timer Interrupt Flag Register
* sbrc r16,TOV0 test the overflow flag (use bit#)
* rjmp TOV0_is_set jump if set
* ... otherwise do something else
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Size: 84992 |
Author: sakthivel |
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Description: 应用VHDL语言设计低频数字频率计，选择测频法方案，主要是控制电路，由其产生闸门、清零和锁存等信号。-VHDL, design low frequency digital frequency meter, select the frequency method to program, mainly the control circuit, produced by the gate and the latch so clear signal.
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Size: 439296 |
Author: 付晓 |
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Description: 本次做的数字日历是以单片机（AT89C51）为核心，结合相关的元器件（共阴极LED数码显示器、BCD-锁存/7段译码/驱动器74LS164等），再配以相应的软件，达到制作简易数字日历的目的，其硬件部分难点在于元器件的选择、布局及焊接。-The figures do bell on SCM (AT89C51) at the core, Combined with the components (a total of cathode LED digital display, BCD- latch /7 of decoding/actuator 74LS164), and factoring in the corresponding software, Easy to produce digital clock purposes, as part of the hardware components is a difficult choice, layout and welding.
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Size: 140288 |
Author: c51com |
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