Search - latch - CodeBus

[Software Engineering] kaitibaogao

Description: 实现CPLD对数据选择器，A/D转换器，锁存器及DPRAM的控制-CPLD implementation of the Data Selector, A/D converter, the control latch and DPRAM
Platform: | Size: 11264 | Author: 李树龙 | Hits:

[SCM] 478195623187

Description: 单片机八路数码抢答器设计，编码电路锁存电路译码电路显示电路-Eight-way digital Responder MCU design, coding circuit latch circuit decoding circuit display circuit
Platform: | Size: 1367040 | Author: 陈琪 | Hits:

[VHDL-FPGA-Verilog] Verilogexample

Description: verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator-verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6 . The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator ....
Platform: | Size: 30720 | Author: vkiy | Hits:

[Documents] shuzi

Description: 设计一个采用数字电路实现,对时,分,秒.数字显示的计时装置,周期为24小时，显示满刻度为23时59分59秒，并具有校时功能和报时功能的数字电子钟。电路主要采用中规模集成电路.本系统的设计电路由脉冲逻辑电路模块、时钟脉冲模块、时钟译码显示电路模块、整电报时模块、校时模块等部分组成。采用电池作电源，采用低功耗的芯片及液晶显示器，发生器使用石英晶振、计数振荡器CD4060及双D触发器74LS74，计数器采用同步双十进制计数器74LS160，锁存译码器是74LS248，整电报时电路用74LS74，74LS32及扬声器构成。-Design a digital circuit, on the hours, minutes, seconds. Figures show that the timing device, 24-hour period, indicating full scale is 23:59:59 and the time with school functions and timekeeping functions of digital electronic clock. Scale integrated circuits used in the main circuit. The design of this system by the pulse logic circuit module, clock module, the clock display circuit decoding module, when the entire cable module, the campus module components. Using a battery powered, low-power chips and liquid crystal display generator using a quartz crystal oscillator, count of CD4060 oscillator and two D flip-flop 74LS74, two-decimal counter synchronous counter 74LS160, latch decoder is the 74LS248, the whole When telegraph circuits 74LS74, 74LS32 and loudspeaker
Platform: | Size: 449536 | Author: 张龙 | Hits:

[Embeded-SCM Develop] MCU_Design_traffic_lights

Description: 本次设计为十字路口交通灯控制系统设计,硬件部分它以8031单片机为核心,并在此基础上扩展了程序存储器（EPROM）2764、静态数据存储器（SRAM）6264，利用地址锁存器74LS373扩展I/O并行接口芯片8255A。软件部分它结合定时/计数等知识进行程序编译。-The design for the intersection traffic light control system design, hardware components it to 8031 as the core, and on this basis, expanded program memory (EPROM) 2764, static data memory (SRAM) 6264, extended use of address latch 74LS373 I/O parallel interface chip 8255A. It combines the software part of the timer/counter and other knowledge to compile.
Platform: | Size: 43008 | Author: jk | Hits:

[Software Engineering] ver1.0

Description: Shutdown of the UC1842 can be accomplished by two methods either raise pin 3 above 1 V or pull pin 1 below a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this pint the reference turns off, allowing the SCR to reset.-Shutdown of the UC1842 can be accomplished by two methods either raise pin 3 above 1 V or pull pin 1 below a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this pint the reference turns off, allowing the SCR to reset.
Platform: | Size: 1024 | Author: prxbl | Hits:

[SCM] 8155

Description: 8155是作为输入输出以及RAM扩充的IC.特性如下： 256字节的RAM。一组可编程6位IO口。两组可编程8位IO口。可编程14位二进制计时计数器。多工地址和数据总线。内部地址锁存。8155采用40脚双列直插封装，单一＋5v电源。-8155 as input and output, and RAM expansion of IC. Features: 256 bytes of RAM. A programmable six IO port. Two programmable 8-bit IO port. 14-bit binary counter programmable timer. Multiplexing address and data bus. Internal address latch. 8155 in a 40-foot two-line package, single+5 v power.
Platform: | Size: 173056 | Author: liuxiao | Hits:

[VHDL-FPGA-Verilog] NCLPROJECT

Description: The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconﬁ gurable logic element are implemented one without extra embedded registration and the other with extra embedded registration. The one with extra embedded registration requires an additional latch but reduces the computing time considerably. Both these versions can be configured as any one of the 27 fundamental NCL gates, including the resettable and inverting variations. The two approaches are compared with each other showing that the version with extra embedded registration requires less computing time than the version without extra embedded registration. -The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconﬁ gurable logic element are implemented one without extra embedded registration and the other with extra embedded registration. The one with extra embedded registration requires an additional latch but reduces the computing time considerably. Both these versions can be configured as any one of the 27 fundamental NCL gates, including the resettable and inverting variations. The two approaches are compared with each other showing that the version with extra embedded registration requires less computing time than the version without extra embedded registration.
Platform: | Size: 6144 | Author: Nagendran | Hits:

[Com Port] 7

Description: 既昨天的430串口程序后又添加了几个程序模块。3*4的矩阵键盘扫描以及通过锁存器IO口复用来驱动数码管。功能是这样：先对按键进行消抖，然后判断键值通过数码管显示通过串口发送出去。-Both procedures after yesterday' s 430 serial port to add a few program modules. 3* 4 matrix keyboard scanning and recovery through the latch to drive the digital IO port tube. Function is this: first, the elimination of key shake, and then determine the key through the digital display through the serial port to send out.
Platform: | Size: 22528 | Author: 小贾 | Hits:

[SCM] 165fehhtyjuk

Description: ATmega48/88/168的PB5是SPI时钟输出，接74HC595/74HC165的移位时钟输入端；PB4是SPI的MISO数据输人，接74HC165的数据输出；PB3是SPI的MOSI数据输出，接74HC595的串行数据输入端SER；PB2接74HC595/74HC165的锁存时钟输入端。 -ATmega48/88/168 the PB5 is the SPI clock output, then 74HC595/74HC165 shift clock input PB4 is the MISO SPI data input, data output connected 74HC165 PB3 SPI, MOSI is the data output, then the string of 74HC595 line data input SER PB2 access 74HC595/74HC165 latch clock input.
Platform: | Size: 2048 | Author: shirley | Hits:

[VHDL-FPGA-Verilog] adder2

Description: 此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。-This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.
Platform: | Size: 1024 | Author: 王柔毅 | Hits:

[SCM] dongtailed

Description: 单片机实现动态显示，为了少用I/O口，用锁存器控制-MCU dynamic display, in order to use less I/O port with latch control
Platform: | Size: 21504 | Author: yang | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL上百实例包括 ADDER LATCH FIPPER AND ETC-VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..
Platform: | Size: 311296 | Author: yuxiang | Hits:

[Embeded-SCM Develop] 62256

Description: 单片机读写62256的程序，硬件连接是单片机的wr脚和rd引脚分别接62256的OE和CS，这两个脚的时序单片机是由硬件自动完成的，P0口作为数据和地址用，用74hc573进行地址锁存，ALE来控制，ALE控制573的时序也是由单片机硬件自动完成的-Microcontroller to read and write 62 256 procedures, the hardware connection is microcontroller rd wr feet and then 62,256, respectively, the OE pin and CS, the timing of these two legs microcontroller is done automatically by the hardware, P0 port as data and addresses, with 74hc573 the address latch, ALE to control, ALE timing control 573 is done automatically by the microcontroller hardware
Platform: | Size: 3072 | Author: 陈泽群 | Hits:

[SCM] qdq

Description: 数字抢答器由主体电路与扩展电路组成。优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出；用控制电路和主持人开关启动报警电路，以上两部分组成主体电路。通过定时电路和译码电路将秒脉冲产生的信号在显示器上输出实现计时功能，构成扩展电路。经过布线、焊接、调试等工作后数字抢答器成形。-Digital Responder extended from the main circuit and the circuit. Priority encoder circuit, latch, decoder circuit will be the team' s output on the display input signal with the control circuit and the host switch to start the alarm circuit, the above two parts of the main circuit. Timing circuit and decoding circuit through second pulse signal to the monitor output to achieve the timing function, constitute the expansion of the circuit. After wiring, welding, testing and other work forming digital Responder.
Platform: | Size: 240640 | Author: 廖生 | Hits:

[VHDL-FPGA-Verilog] 4-10-VHDL-f1

Description: 四位10进制VHDL频率计设计说明四位频率计的结构包括一个测频率控制信号发生器、四个十进制计数器和一个十六位锁存器（本例中所测频率超过测频范围时有警示灯）。-Four 10-digit frequency counter VHDL design description of the structure of the four frequency meter includes a measuring frequency control signal generator, four decimal counter and a sixteen bit latch (in this case the measured frequency over a frequency measurement range warning lights).
Platform: | Size: 54272 | Author: 韦昊斯 | Hits:

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