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Description: 本系统由单片机及其最小系统模块、热电偶测温模块、AD620信号放大模块、键盘模块、LED时钟显示模块、LCD图形显示模块、串口通讯模块组成。可以实现对多点温度的实时测量、分时显示，用户可以通过键盘选择需要显示的通道，也可以通过计算机上的用户界面查看温度变化，强大的显示功能给用户一个直观的印象。-?? ε ? ??? ??? ? Сε ? ?? dawdle ??煼? ? ?? dawdle AD620?? ?? ?? dawdle?? dawdle LED ? ? ? ?? dawdle LCD ? ?? ? ?? dawdle??? ?? ??? latch? ɡ?? ? ?? π? ? ? ?? ? ?? ?? ? ???-? ? ??? ???? ? ????? ? Ш?? ?? ????? ?? ? ????? ???? trouble? ? ?? ?仯?? ?? ?? ???? ??? ??? 5ē? ???
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Size: 789504 |
Author: 陈金豹 |
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Description: 自己写的锁存器程序，用VHDL语言实现，望大家指教-Wrote it myself latch procedures, using VHDL language, hope everyone advice
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Size: 1024 |
Author: chinaafxp |
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Description: DA 输出地址0x20400000
由于DAC0832要求输出锁存保持1uS左右
但CPU在读写（对应nGCS4）写信号最大只能到100ns左右
所以外面加了一个地址锁存74573，573锁存下降沿有效（现在是上升沿有效，也可用）
现在电阻不变的情况下，输出0x00，DA输出0V，输出0xff，DA输出1.7V左右-DA output address 0x20400000 requirements as a result of DAC0832 output latch to keep the CPU in 1uS about reading and writing (corresponding nGCS4) can only write to the 100ns maximum signal around the outside so the addition of an address latch latched falling edge effective 74573,573 (now is the rising edge of effective, can also be used) is now resistance remain unchanged, the output 0x00, DA output 0V, output 0xff, DA output around 1.7V
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Size: 358400 |
Author: aaaa |
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Description: 计数器
锁存器
12位寄存器
带load，clr等功能的寄存器
双向脚（clocked bidirectional pin）
一个简单的状态机
一个同步状态机
用状态机设计的交通灯控制器
数据接口
一个简单的UART
测试向量（Test Bench）举例：
加法器源程序 相应加法器的测试向量test bench）-Counter latch 12 registers with load, clr functions such as two-foot register (clocked bidirectional pin) a simple state machine synchronous state machine with a state machine design data interface controller traffic lights a simple UART test vectors (Test Bench), for example: source corresponding adder adder test bench test bench)
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Size: 11264 |
Author: |
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Description: 简易数字频率计利用复杂可编程逻辑器件FPGA,VHDL编程将所有功能模块集成在一块芯片上。功能模块包括时基脉冲发生器、计数器、数据锁存器和显示电路4部分。设计时先分别设计各功能模块，并调试得到正确仿真结果，然后将各个功能模块组合起来。最后作整体仿真、下载，得到实物。由于采用纯数字硬件设计制作，稳定性、可靠性远远高于使用单片机或模拟方式实现的系统，外围电路简单。该数字频率计达到预期要求，实现了可变量程测量，测量范围0.1Hz—9999MHz，精度可达0.1Hz。-Simple digital frequency meter using complex programmable logic device FPGA, VHDL programming integration of all functional modules on a single chip. Functional modules, including time-base pulse generator, counters, and display data latch circuit 4. Design before the design of various functional modules, respectively, and debugging simulation results correctly, and then combine the various functional modules. Finally, for the overall simulation, download, be kind. As a result of the production of digital hardware design, stability, reliability is far higher than the use of single-chip microcomputer or analog means of the system, a simple peripheral circuits. The digital frequency meter to achieve the desired requirements of the variable-range measurement, measuring range 0.1Hz-9999MHz, accuracy up to 0.1Hz.
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Size: 412672 |
Author: 严术骞 |
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Description: 用 Atmega8 实现D触发锁存器的功能-Atmega8 triggered by the realization of D latch function
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Size: 2048 |
Author: dsgsdg |
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Description: 本次设计中以单片机的发展过程和发展方向为背景，介绍了单片机的输入输出的工作原理和操作方法，中断的工作原理和操作方法。4511的工作原理和操作方法，LED的内部结构。电路设计及调试过程。
本次做的数字钟是以单片机（AT89C51）为核心，结合相关的元器件（共阴极LED数码显示器、BCD-锁存/7段译码/驱动器CC4511等），再配以相应的软件，达到制作简易数字钟的目的，其硬件部分难点在于元器件的选择、布局及焊接。
-The design of a single-chip development process and the development direction for the background, introduced the single-chip input and output of the working principle and method of operation, interruption of the working principle and method of operation. 4511 the working principle and method of operation, LED s internal structure. Circuit design and debugging process. To do this is based on single-chip digital clock (AT89C51) as the core, combined with related components (common cathode LED digital display, BCD-latch/7 segment decoder/driver CC4511, etc.), together with the corresponding software to create simple digital clock The purpose of the hardware part of the difficulties lies in the choice of components, layout and welding.
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Size: 1253376 |
Author: thocr |
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Description: 1. 课程设计的任务
本次课程设计的任务是实现一个算术逻辑运算单元，使之能够完成不带进位位算术、逻辑八位二进制数的运算。由具有扩展能力强，结构简单清晰，连线方便快捷的总线结构作为系统结构。系统测试采用在系统的每个总线上设置测试孔。采用闪存存储数据，系统可以通过监测模块来修改和控制微程序的运行。
采用若干种类的芯片组作为运算器和数据输入输出缓冲、输入锁存器，其中2片74LS181构成8位字长的ALU单元是算术逻辑运算单元核心。
-1. The task of curriculum design curriculum design of this task is the realization of an arithmetic logic operation unit, so that it can not be brought into complete bit-bit arithmetic, logic 8 binary arithmetic. Expansion of capacity by a strong, clear and simple structure, convenient bus connection structure as the system architecture. System test bus in the system set up for each test hole. Store data using flash memory, the system can monitor the module to modify and control the operation of micro-procedures. The use of certain types of chipsets as a computing device and data input and output buffering, input latch, which constitute two 74LS181 word length of 8 is the arithmetic logic unit ALU FPU core.
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Size: 794624 |
Author: xwy1985s |
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Description: 通讯接口协议，发送CDT规约，接受五防协议，闭锁操作-Communication interface protocol, sending CDT Statute and accept the five anti-agreement, latch-up operation
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Size: 5743616 |
Author: |
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Description: 各种电子器件管脚图,THD-1型数字电路实验箱简介,门电路及参数测试,半加器、全加器,数据选择器,数码比较器,译码器和数码显示器,锁存器和触发器,中规模计数器,双向移位寄存器,三态门和数据总线,半导体存储器,多谐振荡器,单稳态触发器,CMOS门电路及集成施密特触发器,集成数模转换器(DAC),逐次渐进型模数转换器(ADC)-Pin diagram of various electronic devices, THD-1 Digital circuit experiment box profiles, gate circuit and the parameters of testing, half adder, full adder, data selector, a digital comparator, decoder and digital display latch and flip-flops, counter scale, bi-directional shift register, three-state gate and data bus, semiconductor memory, Multivibrator, monostable multivibrator, CMOS gate circuits and integrated Schmitt trigger, integrated digital-analog conversion browser (DAC), successive progressive ADC (ADC)
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Size: 707584 |
Author: zl |
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Description: 单字右移1616点阵右移C程序16bit
#include<reg51.h>
#include<intrins.h>
sbit DAT=P1^0 /*"74HC595第14脚 数据 ",0*/
sbit YW=P1^1 /*"74HC595第11脚 移位存 ",0*/
sbit SUO=P1^2 /*"74HC595第12脚 锁存 ",0*/-1616 shifted to right word lattice shifted to right C procedures 16bit# Include <reg51.h># Include <intrins.h> sbit DAT = P1 ^ 0/* 74HC595 foot section 14 data , 0*/sbit YW = P1 ^ 1/* 74HC595 shift foot section 11 deposit , 0*/sbit SUO = P1 ^ 2/* 74HC595 latch pin No. 12 , 0* /
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Size: 2048 |
Author: z |
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Description: 点阵上滚显示20字./*点阵显示汉字程串口输出字符数据，P2口输出行扫描信号,P0_0输出595锁存信号。
由于595接在LED阴极所以取模时要反白处理*/-Dot matrix display 20 characters on the roll./* Dot-matrix display Chinese characters-way serial output character data, P2 I scan signal output line, P0_0 latch 595 output signal. Then as a result of 595 in the LED cathode so modulus to deal with anti-white* /
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Size: 2048 |
Author: z |
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Description: 本程序实现了一个数字频率计。它由一个测频控制信号发生器TESTCTL，8个有时钟的十进制计数器CNT10，一个32位锁存器REG32B组成。-This procedure implements a digital frequency meter. It consists of a frequency control signal generator TESTCTL, 8 which have the metric system clock counter CNT10, a 32-bit latch REG32B component.
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Size: 1024 |
Author: liushenshen |
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Description: 用VHDL实现数字频率计,1. 时基产生与测频时序控制电路模块2. 待测信号脉冲计数电路模块3.锁存与译码显示控制电路模块4.顶层电路模块.
-Using VHDL digital frequency meter, 1. Time-base generation and frequency measurement timing control circuit module 2. Analyte signal pulse counting circuit module 3. Latch and decoding display control circuit module 4. Top-level circuit module.
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Size: 13312 |
Author: 侯治强 |
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Description: 数字抢答器由主体电路与扩展电路组成。优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出；用控制电路和主持人开关启动报警电路，以上两部分组成主体电路。通过定时电路和译码电路将秒脉冲产生的信号在显示器上输出实现计时功能，构成扩展电路。经过布线、焊接、调试等工作后数字抢答器成形。-Answer the number is controlled by the main circuit and the expansion of circuit components. Priority encoder circuit, latch, decoder circuit will be teams of the input signal in the display output with control circuitry and the host switch alarm circuits, and above the main circuit is composed of two parts. Through the timing circuit and decoding circuit to generate pulse signals in the display output timing realize functions, constitute the expansion of the circuit. After wiring, welding, debugging, etc. Answer device forming after the figures.
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Size: 56320 |
Author: WHSAH |
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Description: 1. 一秒定时的实现。
设定定时器每100us中断一次，在中断服务程序中，对中断次数进行计数，计数10000次就是1秒。
2.分、秒的显示
用四个数码管配合373芯片的锁存功能就可以完整地显示分、秒信息。373芯片的片选则需要138芯片的译码和04芯片的取反。
3. 调时的实现
利用单片机的外部中断和三个按键，我们可以方便的实现调时功能。比如三个按键开关产生的中断信息可以分别用于“开始（停止）调时”、“选择调时位”、“当前选择位+1”。
4. 实现按键的软件去抖动功能。
-1. The realization of a second timing. Set a timer interrupt every 100us, in the interrupt service routine, the number of interruptions to count, count 10000 times is 1 seconds. 2. Minutes and seconds are displayed using four digital tube 373 with the latch function of the chip can be a complete display minutes and seconds information. 373 chip-chip election would require 138 of the decoding chip and 04 chips from the anti-. 3. Tune realize single-chip computer at the time of the external interrupt and three buttons, we can realize a convenient function when transferred. For example, three button switches interrupt generated information can be used for
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Size: 1024 |
Author: li |
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Description: 含异步清0和同步时钟使能的4位加法计数器
含计数使能,异步复位和计数值并行预置功能4位加法计数器,由实验图1所示,图中间是4位锁存器 rst是异步清信号,高电平有效 clk是锁存信号 D[3..0]是4位数据输入端.当ENA为 1 时,多路选择器将加1器的输出值加载于锁存器的数据端 当ENA为 0 时将"0000"加载于锁存器.-With asynchronous and synchronous clock clearance 0 enabled four adder counter with count enable, asynchronous reset and preset functions of numerical parallel adder four counters, by the experiment shown in Figure 1, Figure 4 middle latch rst is asynchronous clearance signal, high effective signal clk is Latched D [3 .. 0] is 4-bit data input. When ENA for 1:00, MUX will increase the output value of 1 load in latch data terminal when the ENA for the 0:00 to 0000 add-in latch.
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Size: 63488 |
Author: 黄杰深 |
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Description: 点阵显示汉字程串口输出字符数据，P2口输出行扫描信号,P0_0输出595锁存信号-Dot-matrix display Chinese characters-way serial output data, P2 I scan signal output line, P0_0 latch 595 output signal
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Size: 1024 |
Author: 胡旭东 |
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Description: 由8051组成的单片机系统通常情况下，P0口分时复用作为地址、数据总线，P2口提供A15-A8即高8位地址，P3口用作第二功能，只有P1口通常用作I/0口。P1口是8位准双向口，它的每一位都可独立地定义为输入或输出，因此既可作为8位的并行I/O口，也可作为8位的输入输出端。当工作在输入方式时，对应位的锁存器必须先置1,才能正确地读到引脚上的信号,否则,执行读引脚指令时,若对应位的锁存器的值为0，读的结果永远为0。-By 8051, composed of single-chip microcomputer system under normal circumstances, P0 timeshare I reuse as address, data bus, P2 I provide A15-A8 high eight address, P3 mouth for the second function, I usually only P1 for I/0 I. P1 I was eight quasi-two-way port, it can be independent of each and every defined as input or output, it can be used as 8-bit parallel I/O port, can also be used as 8-bit input and output side. When the work in the input, the corresponding bit latch must first buy one in order to correctly read the signal pin, or pin the implementation of reading instruction, if the corresponding bit latch the value of 0, Reading the results of Forever to 0.
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Size: 1024 |
Author: 张理 |
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Description: 一个使用单片机实现四路触发锁存器的程序，可供初学者学习单片机模拟逻辑芯片的一些简单功能。-MCU four trigger latch program for beginners to learn some simple the microcontroller analog logic chip functions.
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Size: 2048 |
Author: pzhihui |
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