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Description: Single SR-Latch For Pic 16F84A
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Size: 14336 |
Author: lmilmi |
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Description: 4 Bit Latch for pic 16f84a
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Size: 12288 |
Author: lmilmi |
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Description: this document have 5 program in vhd format..
mealy program,ram,comparator,latch, and static ram
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Size: 2048 |
Author: zack |
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Description: 该程序完成8位数码管的动态显示，显示内容为YOURNUMBER表格中的数字。
数码管为共阳数码管，由P0口提供段码和位选信号，P0口的输出由段码锁
存器和位选锁存器控制，段码锁存器的控制信号来自于P1.3，位选锁存器
的控制信号来自于P1.2。-The process is complete 8-bit dynamic digital display, display table numbers for the YOURNUMBER. LED digital tube for a total positive, provided by the P0 port section of code and bit-select signal, P0 port output latch by a section of code and bit latch select control, Segment latch control signal from the P1. 3, the bit latch select control signal from P1.2.
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Size: 1024 |
Author: leo |
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Description: vhdl code for the function of performing latch and flipflop.-vhdl code for the function of performing latch and flipflop.
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Size: 1384448 |
Author: aryan |
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Description: ADC0809 是8 位逐次逼近型A/D转换器。它由一个8路模拟开关、一个地址锁存译码器、一个A/D 转换器和一个三态输出锁存器组成（见图1）。多路开关可选通8个模拟通道，允许8 路模拟量分时输入，共用A/D 转换器进行转换。三态输出锁器用于锁存A/D 转换完的数字量，当OE 端为高电平时，才可以从三态输出锁存器取走转换完的数据。-ADC0809 8-bit successive approximation A/D converter. It consists of an 8-channel analog switch, an address latch decoder, an A/D converter and a three-state output latch (see Figure 1). Multi-switch selectable through eight analog channels, allowing time-8 analog inputs, common A/D converter to convert. Three-state output latch lock is used for A/D converting the digital value, when the OE terminal is high, it can be from the tri-state output latch removed converting the data.
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Size: 226304 |
Author: lanying |
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Description: 当P0作为I/O口使用时，特别是作为输出时，输出级属于开漏电路，必须外接上拉电阻才会有高电平输出；如果作为输入，必须先向相应的锁存器写“1”，才不会影响输入电平。-When P0 as the I/O port to use, especially as the output, open drain output stage circuit is to be an external pull-up resistor will have a high output if, as input, the corresponding latch must first write " 1 " , it will not affect the input level.
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Size: 3072 |
Author: 周滨彬 |
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Description: 病房呼叫系统 锁存器 计时模块 优选模块 时间模块-Ward calling system timing module latch time module selection module
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Size: 10240 |
Author: 北堂傲天 |
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Description: 一个锁存器，单纯简单的，没什么好用的，以后再穿好的上来-A latch, simple simple, nothing easy to use, wear good up after
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Size: 221184 |
Author: 涨势 |
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Description: 89C51
1.基本功能：
（1） 同时供8名选手比赛，分别用8个按钮S0 ~ S7表示。
（2）设置一个系统清除和抢答控制开关S，该开关由主持人控制。
（3）抢答器具有锁存与显示功能。即选手按动按钮，锁存相应的编号，扬声器发出声响提示，并在七段数码管上显示选手号码。选手抢答实行优先锁存，优先抢答选手的编号一直保持到主持人将系统清除为止。
2.扩展功能：
（1）抢答器具有定时抢答功能，且一次抢答的时间由主持人设定（如30秒）。当主持人启动"开始"键后，定时器进行减计时。
（2）参赛选手在设定的时间内进行抢答，抢答有效，定时器停止工作，显示器上显示选手的编号和抢答的时间，并保持到主持人将系统清除为止。（3）如果定时时间已到，无人抢答，本次抢答无效，系统报警并禁止抢答，定时显示器上显示00。
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89C51
1. The basic functions:
(1) also for 8 contestants race, respectively for eight buttons S0 ~ S7 said.
(2) set up a system to eliminate and vies control switch S, this switch controls by the director.
(3) contest appliances have latch and display function. Namely player at the press of a button, latch corresponding Numbers, speaker hint and sound in seven segment digital tube demonstrated contestant number. Contestant vies to answer first the implementation first latch, first vies to answer first contestant s Numbers keep to the director the system elimination up to date.
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Size: 190464 |
Author: han |
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Description: D-type storage elements
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.-D-type storage elements
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.
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Size: 3438592 |
Author: sunyan |
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Description: 这是用AT89s51做的一个简单电子钟，它有六个LED数码管组成，HC573作为锁存器，电路较为简单，适于初学者应用！-This is done with a simple AT89s51 clock, it has six LED digital tubes, HC573 as a latch, the circuit is simple, suitable for beginners application!
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Size: 194560 |
Author: boyalittle |
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Description: 测频控制 锁存器 计数器 顶层文件 -Frequency counter top-level file control latch
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Size: 4096 |
Author: |
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Description: 本例子是用硬件SPI接口循环发送一个变量到74HC595，并且在数据发送完毕后通过单片机的另外一个IO接口PB2输出一个“锁存”脉冲 ，使74HC595把移位寄存器的数据输出到锁存寄存器,并驱动8个LED输出，实现来回流水的效果。-This example is using the hardware SPI interface to send a variable to the loop 74HC595, and after the data is sent through the microcontroller interface to another IO PB2 output a " latch" pulse, the 74HC595 shift register to latch the data output to the register, and drive 8 LED outputs, to achieve the effect of water back and forth.
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Size: 5120 |
Author: 张玉坤 |
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Description: 锁存器机及其激励内容包含锁存器程序及其激励程序朗朗上口-latch and it s jili prosursor，very good simulation,useful ziliao
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Size: 1024 |
Author: 李刚 |
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Description: 这是锁存器的基本应用，希望能给初学者点帮助-This is the latch of the basic applications, I hope to give some help for beginners
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Size: 16384 |
Author: WADE |
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Description: 数字设计课件ppt，基本的门，译码器，编码器，多路复用器，比较器，锁存器，触发器等-Digital design courseware ppt, basically the door, decoder, encoder, multiplexer, comparator, latch, trigger, etc.
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Size: 15145984 |
Author: 刘备 |
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Description: 4个移位锁存器HC595驱动，带锁存和输出使能-4 HC595-driven shift latch with latch and output enable
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Size: 1024 |
Author: 吴玉锋 |
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Description: 数字抢答器① 用EDA实训仪的I/O设备和PLD芯片实现智能电子抢答器的计。
② 智能电子抢答器可容纳4组参赛者抢答，每组设一个抢答钮。
③ 电路具有第一抢答信号的鉴别和锁存功能。在主持人将复位按钮按下后开始抢答，并用EDA实训仪上的八段数码管显示抢答者的序号，同时扬声器发出“嘟嘟”的响声，并维持3秒钟，此时电路自锁，不再接受其他选手的抢答信号。
④ 设计一个计分电路，每组在开始时设置为100分，抢答后由主持人计分，答对一次加10分，答错一次减10分。
⑤ 设计一个犯规电路，对提前抢答和超时抢答者鸣喇叭示警，并显示犯规的组别序号。
-① The EDA training instrument I/O devices and PLD chip intelligent electronic Responder count.
② intelligent electronic Responder Responder can accommodate four participants, each with an answer in button.
③ circuit with the first answer in the identification signal and latch functions. The host will begin to answer in the reset button is pressed, and instrument training with EDA eight out digital display on the Responder s serial number, and the speaker issued a "beep" sound, and maintained for 3 seconds, and the circuit from lock, no longer accept other players answer in the signal.
④ design a scoring circuit, at the beginning of each set of 100 points, answer the points after the host, answer a plus 10 points, got it wrong again by 10 points.
⑤ circuit design a foul, the answer in and time out to answer in advance by honking warning, and display groups of foul number.
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Size: 2194432 |
Author: wtm_dxyb |
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Description: ARM7内核芯片LPC2104部分源程序
名 称：多功能点阵显屏
功 能：显示文字，时间，图形等
说 明：74HC154做行扫描，74HC164做列数据经74LS373锁存输出由ULN2803A驱动点亮LED,-LPC2104 ARM7-core chip part of the source name: Multi-function dot-matrix display screen: display text, time, graphics and other instructions: 74HC154 do line scan, 74HC164 74LS373 latch to do the column data output by the light from the ULN2803A drive LED,
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Size: 18432 |
Author: 杨浩 |
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