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Description: 1、用feng模块将选手按下按键信号输出高电平给锁存模块lockb，进行锁存的同时发出aim信号实现声音提示，并使count模块进行答题时间的倒计时，在计满100妙后送出声音提示；
2、用ch41a模块将抢答结果转换为二进制数；
3、用sel模块产生数码管片选信号；
4、用ch42a模块将对应数码管片选信号，送出需要的显示信号；
5、用七段译码器dispa模块进行译码。 -1, using feng module will press a key player to a high signal output latch module lockb, issued at the same time to latch the signal aim to achieve prompt voice and answer module count of the countdown time, taking into account the post-Miao 100 sent the voice prompts 2, with the results of ch41a Answer module will convert the binary number 3, with sel digital control module chip select signal 4, with ch42a digital control module to the corresponding chip select signal, the display need to send signal 5, Seven-Segment Decoder with dispa decoding module.
Platform: |
Size: 2048 |
Author: 张漠然 |
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Description: 四路抢答题，输入可以为四路不同信号，通过锁存抢答信号进行抢答。-Four-way scramble answer, for four different input signals, signals through the latch Answer Answer.
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Size: 1024 |
Author: 柳苏 |
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Description: 简单微型计算机设计
设计一个8088系统，要求接成最大模式。地址锁存器选用74LS373，数据总线收发器用选用74LS245，时钟发生器选用8284，中断控制器选用8259A，总线控制器选用8288。
-Design a simple micro-computer. Design 1. 8088 to design a system, then into the most requested model. Address latch selection 74LS373, selection of data bus transceiver uses 74LS245, optional clock generator 8284, optional interrupt controller 8259A, selected bus controller 8288.
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Size: 241664 |
Author: siren |
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Description: （1）抢答器同时供4名选手比赛，分别用4个按钮S1 ～ S4表示；
（2）设置一个系统清除和抢答控制开关S5，该开关由主持人控制；
（3）抢答器具有锁存与显示功能。即选手按动按钮，锁存相应的编号，选手抢答实行优先锁存，优先抢答选手的编号一直保持到主持人将系统清除。
-(1) Answer 4 simultaneous players for the game, with four buttons, respectively, S1 ~ S4 that (2) to set up a system to remove and Answer control switch S5, the switch from host control (3) has the latch Answer and display functions. That the players push the buttons, the corresponding number of latches, the implementation of priority latch' s Answer, Answer the priority has been to maintain the number of players to clear the host system.
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Size: 1024 |
Author: 离火 |
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Description: 一个基于51单片机的锁存器代码.附带电路图-51 single-chip based on the code of the latch. Incidental circuit
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Size: 106496 |
Author: 李俊男 |
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Description: 32位数据锁存器，用于数据锁存，测试可用，实际使用过-latch，32bits.
Platform: |
Size: 1024 |
Author: 吴次仁 |
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Description: 595连级输出数据，138行驱动。P0_1为移动速度高速/*点阵显示汉字程串口输出字符数据，
//P2口输出行扫描信号,P0_0输出595锁存信号。*/
-Even 595-level output data, 138 line driver. The speed of high-speed mobile P0_1/* dot-matrix display Chinese characters-way serial data output,// P2 I scan signal output line, P0_0 latch output signal 595.* /
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Size: 4096 |
Author: dfas |
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Description: 风力发电设备用CPLD外围控制程序。包括故障锁存，IO口输出输入，地址线译码等。-Wind power generation equipment control procedures external CPLD. Including the fault latch, IO I O, address decoding and other lines.
Platform: |
Size: 73728 |
Author: 吕佃顺 |
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Description: 三路智力竞赛抢答器，利用VHDL设计抢答器的各个模块，并使用EDA 工具对各模块进行仿真验证。智力竞赛抢答器的设计分为四个模块：鉴别锁存模块；答题计时模块；抢答计分模块以及扫描显示模块。把各个模块整合后，通过电路的输入输出对应关系连接起来。设计成一个有如下功能的抢答器：
（1）具有第一抢答信号的鉴别锁存功能。在主持人发出抢答指令后，若有参赛者按抢答器按钮，则该组指示灯亮，数码管显示出抢答者的组别。同时电路处于自锁状态，使其他组的抢答器按钮不起作用。
（2）具有计分功能。在初始状态时，主持人可以设置答题时间的初始值。在主持人对抢答组别进行确认，并给出倒计时计数开始信号以后，抢答者开始回答问题。此时，数码管从初始值开始计时，计至0时停止计数。
（3）具有计分功能。在初始状态时，主持人可以给每组设置初始分值。由主持人打分，答对一次加1分阶段。
（4）扫描显示功能。在初始状态时，各组计分给出一个固定的值并将它扫描显示在数码管上，当计分或者要显示的数据发生变化时，再次扫描并显示出来。
-Answer quiz three-way, and the use of VHDL design of each module s Answer, and the use of EDA tools for simulation of the module. Answer quiz design is divided into four modules: the differential latch module answer time module Answer scoring module and scanning module. The integration of each module through the input and output circuits connect the corresponding relations. Designed as a function of the Answer the following devices:
(1) Answer with the first differential signal latch function. Answer sent in the host command, if the participants by the Answer button, the group of bright lights, digital display of the group Answer. At the same time, the state of the circuit in a self-locking, so that other groups do not work the Answer button.
(2) scoring function. In the initial state, the host can set the initial value of Examination Time. Answer the host of the group to confirm and count the beginning of the countdown signals are given, the Answer to answer questions from the b
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Size: 234496 |
Author: menglj |
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Description: 介绍了ADF4360-8芯片的功能、内部结构、引脚排列及典型的应用电路及其评估板。ADF4360-8是集成的整数N合成器和压控振荡器（VCO）。芯片内嵌一个基准输入部分、N计数器和R计数器、相位频率检波器（PFD）和充电泵、多路复用器和锁定检波器、输入移位寄存器、控制锁存器、N计数锁存器、R计数锁存器。它可用于产生系统时钟，作为测试设备，用于无线局域网（LAN），作为闭路电视（CATV）设备。ADF4360-8EB1评估板可以让用户评估ADF4360-8频率合成器PLL的性能。
-Introduced the ADF4360-8-chip features, the internal structure of a typical pin and the application circuit and its evaluation board. ADF4360-8 is an integrated integer N synthesizer and voltage controlled oscillator (VCO). Input chip embedded part of a benchmark, N and R counters counter, phase frequency detector (PFD) and charge pump, and lock multiplexer detector, input shift register, control latch, N counter latch , R latch count. It can be used to generate system clock, as a test equipment for wireless local area network (LAN), as a closed-circuit television (CATV) equipment. ADF4360-8EB1 evaluation board allows users to assess the ADF4360-8 Synthesizer PLL performance.
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Size: 400384 |
Author: 庄乾章 |
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Description: 用74HC595驱动两个数码管，属于静态显示,
74HC595是一个三态输出8位移位/锁存器,
SCK是时钟输入引脚，接PD6
在SCK的上升沿SER的上的电平信号被读入内部寄存器最底位接PD4
RCK是锁存控制脚，在上升沿内部寄存器的内容被锁存到相应输出脚的锁存器中，接PD5-74HC595 driven by two digital tube, is a static display, 74HC595 is a three-state output 8-bit shift/latch, SCK is the clock input pin, and then in the PD6 the rising edge of SCK on the SER-level signals are read into the most at the end of the internal register access PD4 RCK-bit latch control pin is in the rising edge of the contents of internal registers to be latched to the corresponding output pin of the latch, and then PD5
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Size: 2048 |
Author: 帮主 |
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Description: 数字抢答器由主体电路与扩展电路组成。优先编码电路、锁存器、译码电路将参赛队的输入信号在显示器上输出；用控制电路和主持人开关启动报警电路，以上两部分组成主体电路。通过定时电路和译码电路将秒脉冲产生的信号在显示器上输出实现计时功能，构成扩展电路。经过布线、焊接、调试等工作后数字抢答器成形。-Answer the number of circuits is controlled by the main circuit and expansion. Priority encoder circuit, latch, decoder circuit will be teams of the input signal in the display output with control circuitry and the host switch alarm circuits, and above the main circuit composed of two parts. Through the timing circuit and decoding circuit to generate pulse signals in the display output timing functions, constitute the expansion of the circuit. After wiring, welding, testing, etc. Answer the number of devices after the forming.
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Size: 56320 |
Author: 彭秀媛 |
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Description: (1) 抢答器线路测试功能
为了保证比赛的正常进行，比赛前需要调试线路能否正常工作。
(2) 第一抢答信号的鉴别和锁存功能
可以判断谁最先抢到回答的资格，其相应的绿灯表示抢答成功，并具有锁存功能，一直到下一题开始。
(3) 犯规警示功能
可以判断出参赛者有没有在主持人读题的期间按下抢答器，有则相应的红灯亮，同时取消其本轮抢答资格。
(4) 计时功能
可以预置时间，可以进行倒计时并且将时间显示出来。
(5) 计分功能
可以实现加分，并且显示出来
-(1) Answer line testing device in order to ensure the normal game, the need to debug line before the game can work properly. (2) Answer the first to identify and latch signals to determine who can be the first to get the qualifications to answer, and its corresponding Answer green that success and with latch function, until the beginning of the next title.
(3) foul warning function can be judged contestants have read in the host during the press Answer questions, and there is a corresponding red light, at the same time cancel the current round of qualifications Answer. (4) The time functions can be preset time, the countdown can be displayed and the time. (5) scoring function points can be achieved and displayed.
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Size: 956416 |
Author: 孙国栋 |
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Description: 源码为51单片机所写的74HC573锁存代码，经试验过了，很好用-Source for the 51 single-chip latch 74HC573 written code, as tested, and very good use
Platform: |
Size: 11264 |
Author: 张小小 |
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Description: 4位数字频率计控制，分为锁存、计数等几个模块-4 digital frequency meter control, is divided into latch, counting a number of modules, etc.
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Size: 146432 |
Author: qian |
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Description: 带锁存功能的串入并出芯片。这里给出74hc595的c51驱动程序-With latch function and the string into a chip. Here are the 74hc595 driver c51
Platform: |
Size: 2048 |
Author: zhangqiang |
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Description: 带锁存功能的串入并出芯片。这里给出74hc595的c51驱动程序-With latch function and the string into a chip. Here are the 74hc595 driver c51
Platform: |
Size: 31744 |
Author: zhangqiang |
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Description: MSC-51与外部数据存储器的一般连接方法：外部数据存储器的高8位地址由P2口提供，低8位地址线接地址锁存器的输出端。外部RAM的读、写控制信号分别接MCS-51的 、 。外部RAM的片选信号可由P2口未用的地址线的剩余口线以线选方式或译码方式提供-MSC-51 with the external data memory of the general connection method: external data memory address high 8 provided by the P2 population, low 8-bit Address Address Line output latch. External RAM reading and writing control signals, respectively, then the MCS-51,. External RAM chip select signal may be the P2 I did not address the remainder of the line to line I-line or decoding method of election to provide
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Size: 1024 |
Author: jennycomeon |
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Description: 介绍基于S3C44B0控制的大型LED显示系统。数据传输采用并行总线方式，并提出将LED显示模块厦显示锁存单元虚拟地视为一段连续的存储单元，利用S3C44B0内部DMA控制器进行数据传输和控制，节省使用指令传输数据额外的软件开销，使其具有传输速度快、效率高的特点，以达到用单CPU系统代替多机系统控制LED显示系统的目的。
-S3C44B0 introduced based on the control of large-scale LED display system. Parallel data bus mode, and LED display module will show the latch unit building be regarded as a continuous period of virtual storage unit, the use of S3C44B0 internal DMA controller for data transmission and control, to save data using the command additional software overhead to have a transmission speed, high efficiency, so as to achieve a single CPU system to replace multi-system control purpose LED display systems.
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Size: 165888 |
Author: 打狗队 |
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Description: 这是关于锁存器的vhdl语言。。大家相互交流-This is the latch on the vhdl language. . We each other. .
Platform: |
Size: 3072 |
Author: 于振雨 |
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