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[Software EngineeringBL75R04-keil

Description: BL75R04SM 2K 位EEPROM 射频识别 射频接口完全符合ISO15693标准 该程序可进行数据数据的多读写等操作 BL75R04SM 是遵从 ISO/IEC15693 无线接口的2Kbit 电子标签芯片。可制作成电子 标签或非接触卡,主要适用于大中型物流、商品防盗防伪、工业控制、门禁系统、军 事跟踪、路桥收费、畜牧养殖、图书文档管理、特种设备和金融票据等领域。具备防 2 冲突功能,读写器能同时快速处理多个芯片。片内2K 位 E PROM,分成64block, 每 block 有4 字节的数据存储区,2 个位的块锁存区,管理存储区2 block ,全球唯一 的64 位标示码。 -BL75R04SM 2 K bit EEPROM radio frequency identification Rf interface fully comply with ISO15693 standards This program can be more data data and operation BL75R04SM is follow ISO/IEC15693 wireless interface Kbit electronic tag 2 chip. Can be made into electronic Tag or the contact card, mainly is suitable for the large and medium-sized logistics, commodity anti-theft security, industrial control, access control system, the army Things tracking, road, bridge charges, animal husbandry and breeding, books document management, special equipment and financial instruments, etc. Have the 2 Conflict, literacy can at the same time the function DuoGe rapid processing chip. Within 2 K bit E of PROM, which divided into 64, Every four bytes of data which storage area, two bits of the latch area, the area of storage management, the only global which 2 A mark of 64 yards.
Platform: | Size: 166912 | Author: zakailynn | Hits:

[File FormatBL75R04

Description: 继上次源码开放后,本次把BL芯片信息公开下载,供大家与程序操作 BL75R04SM 是遵从 ISO/IEC15693 无线接口的2Kbit 电子标签芯片。可制作成电子 标签或非接触卡,主要适用于大中型物流、商品防盗防伪、工业控制、门禁系统、军 事跟踪、路桥收费、畜牧养殖、图书文档管理、特种设备和金融票据等领域。具备防 2 冲突功能,读写器能同时快速处理多个芯片。片内2K 位 E PROM,分成64block, 每 block 有4 字节的数据存储区,2 个位的块锁存区,管理存储区2 block ,全球唯一 的64 位标示码。 -BL75R04SM 2 K bit EEPROM radio frequency identification Rf interface fully comply with ISO15693 standards This program can be more data data and operation BL75R04SM is follow ISO/IEC15693 wireless interface Kbit electronic tag 2 chip. Can be made into electronic Tag or the contact card, mainly is suitable for the large and medium-sized logistics, commodity anti-theft security, industrial control, access control system, the army Things tracking, road, bridge charges, animal husbandry and breeding, books document management, special equipment and financial instruments, etc. Have the 2 Conflict, literacy can at the same time the function DuoGe rapid processing chip. Within 2 K bit E of PROM, which divided into 64, Every four bytes of data which storage area, two bits of the latch area, the area of storage management, the only global which 2 A mark of 64 yards.
Platform: | Size: 197632 | Author: zakailynn | Hits:

[Software Engineeringvhdl

Description: 3vhdl简单程序设计;4,8-3优先编码器5,3-8译码器;6,6d锁存器;7,数码管扫描显示;8,四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter
Platform: | Size: 483328 | Author: 绿茶混咖啡 | Hits:

[VHDL-FPGA-Verilog8sc

Description: 8位所存显示延时源代码,较完美诠释锁存艺术-8-bit display delay kept the source code, the more perfect interpretation of the latch Art
Platform: | Size: 548864 | Author: 张冰 | Hits:

[Other Embeded programds18b20

Description: 在数码管上面显示DS18B20转换出来的时间,数码管里面有两个377的锁存器,来控制段选和位选,这个时间可以精确到小数点后面一位.-DS18B20 shown above in the digital conversion out of time, there are two digital latch 377 to control the selection and position selection section, this time can be accurate to one decimal point.
Platform: | Size: 2048 | Author: 陈久 | Hits:

[Software Engineeringskdy

Description: 数控电源,有矩阵键盘中断,快速+/-步进,数码管驱动(带锁存器)。pwm部分请自行调试。-NC Power, a matrix keyboard interrupt, fast+ /- step, the digital drive (with latch). pwm part of your own debugging.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilogadder_latch

Description: 用verilog编写了一段地址锁存器的代码,希望能帮助大家!-Prepared using a verilog code address latch, hoping to help you!
Platform: | Size: 26624 | Author: benzema | Hits:

[SCMLab4

Description: A Light Emitting Diode (LED) is associated with each button and shares the same identification number, except the door-open and door-close LEDs (which use No. 5, see later). Each LED is also driven by a Latch and shares the button circuitry such that if a LED is On, the corresponding switch cannot be sensed.-A Light Emitting Diode (LED) is associated with each button and shares the same identification number, except the door-open and door-close LEDs (which use No. 5, see later). Each LED is also driven by a Latch and shares the button circuitry such that if a LED is On, the corresponding switch cannot be sensed.
Platform: | Size: 248832 | Author: christina | Hits:

[ARM-PowerPC-ColdFire-MIPSLDT

Description: 亮灯条,p89c668,74ls273锁存,ads7816电压采集-Light bar, p89c668, 74ls273 latch, ads7816 voltage acquisition
Platform: | Size: 50176 | Author: zhangyue | Hits:

[SCMdisplay

Description: keil坏境下 STC12C5A系列单片机的数码管显示程序 采用锁存器-keil under bad environment STC12C5A series MCU using digital tube display program latch
Platform: | Size: 27648 | Author: mercury | Hits:

[VHDL-FPGA-VerilogVHDL-language

Description: 用VHDL语言完成4位锁存器、测频控制器的设计-VHDL language to complete 4-bit latch, the measured frequency controller design
Platform: | Size: 1024 | Author: denwei0011 | Hits:

[SCMmobile-remote

Description: bascom-avr源码:用移动电话控制四个继电器。-AVR Cell phone unlimited remote control Project: This is a unlimited remote control system based on GSM mobile phone. this project work with DTMF signals and decode them to control four relays. tehere are several mode like flip flop, latch, etc that controlled by dip switch.
Platform: | Size: 178176 | Author: lupo | Hits:

[SCM25-dsm

Description: 单个数码管静态显示,用锁存器进行控制,需要请留意-Static single digital display, with the latch control, need to pay attention
Platform: | Size: 9216 | Author: sad | Hits:

[VHDL-FPGA-VerilogProgram3

Description: 用 vhdl 语言设计 8 位数码扫描显示电路,显示输出数据直接在程序中给出。增加 8 个 4 位锁存器作为输出显示数据缓冲器,由外部输入8个待显示的十六进制数。-Design with vhdl language display 8-bit digital scanning circuit, display output data are given directly in the program. Increased eight 4-bit latch display data buffer as the output from the external input 8 to be displayed in hexadecimal.
Platform: | Size: 1024 | Author: 釉雪Dreamer | Hits:

[VHDL-FPGA-Veriloglesson3-2

Description: 用一根导线连接在P3.2和GND之间,使P3.2为低电平。那么进入中断 既是第一个二极管闪一下 ,进而 程序继续进行 它与电平触发不一样。 总结: 若采用电平触发方式,外部中断申请触发器的状态随着CPU在每个机器周期采样到的外部 中断输入线的电平变化而变化,这能提高CPU对外部中断中断请求的响应速度。当 外部中断源设定为电平触发方式时,在中断服务程序返回之前,外部中断请求 输入必须是无效的(既变为高电平)否则CPU返回主程序之后会再次响应中断。(也即是主程序不在执行) 所以电平触发方式适合于外部中断以低电平输入而且中断服务程序能清除外部中断请求源。 而若采用跳变沿触发时,外部中断申请触发器能锁存外部中断输入线上的负跳变,即便是 CPU暂时不能响应,中断申请标志也不会丢失,在这种方式里 如果相继连续两次采样,一个机器周期采样到外部中断输入为高,下一个机器 周期采样为低,则置1.中断申请触发器,直到CPU响应此中断时才清0,这样才不会 丢失中断,但输入的负波冲宽度至少保持12个时钟周期才能被CPU采样到,因此适合于 以负脉冲形式输入的外部中断请求。 -With a wire connected between P3.2 and GND, so P3.2 is low. Then enter the interrupt Is the first diode flash, then the program continues It is not the same with the trigger level. Summary: The use of a level-triggered mode, the external interrupt request flip-flop state with the CPU in each machine cycle to the external Interrupt input line level changes, which can improve the CPU interrupt request to the external interrupt response time. When the External interrupt source is set to level-triggered mode, the interrupt service routine returns, the external interrupt request Input must be invalid (both high) or the CPU returns to the main program after the interrupt again. (That is the main program is not running) Therefore, the level triggered mode is suitable for low-level input and external interrupt to the interrupt service routine to clear the external interrupt request source. The use of a transition edge trigger, the external interrupt request flip-flop to latch
Platform: | Size: 1024 | Author: 王伟 | Hits:

[VHDL-FPGA-Verilogmulti8x8

Description: 该源码为8位乘法器的VHDL语言描述,由一个8位右移寄存器,2个4位加法器例化成8位加法器,一个16位数据锁存器构成。采用移位相加的方式,从被乘数的低位开始,与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit adder, a 16-bit data latch form. Using the sum of the shift, from a low starting multiplicand, the multiplier for each bit shift and summed. Finally, to achieve its multiplier function.
Platform: | Size: 393216 | Author: feng | Hits:

[OS DevelopDETSPFF1

Description: This paper describes a hybrid latch-flipfl op (HLFF) timing meth- odology aimed ... HLFF is similar to standard fl ip-fl ops in that it samples the data on one edge of
Platform: | Size: 4096 | Author: sakthivel | Hits:

[SCMEV1527-PIC

Description: 无线接收解码源程序。 可学习解码。锁存输出功能。-Wireless receiver decoder source code. Can learn decoding. Latch output.
Platform: | Size: 40960 | Author: sdfsdf | Hits:

[VHDL-FPGA-VerilogROM-based-sine-wave-generator-design

Description: 设计基于ROM的正弦波发生器,对其编译,仿真。 具体要求: 1.正弦发生器由波形数据存储模块(ROM),波形发生器控制模块及锁存模块组成 2.波形数据存储模块(ROM)定制数据宽度为8,地址宽度为6,可存储 64点正弦波形数据,用MATLAB求出波形数据。 3.将50MHz作为输入时钟。-ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch module 2 waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64 point sine wave data, waveform data obtained using MATLAB. 3 to 50MHz clock as input.
Platform: | Size: 65536 | Author: 坐听晚风赏晚霞 | Hits:

[SCMButtons-control

Description: 按键控制数码管显示的程序。包括proteus仿真电路图。功能是通过按键的次数实现不同的灯的控制,虽然功能简单,但是使用了片选、锁存,可以作为单片机I/O通过片选扩展端口的很好的例子。自己正在学习编程,希望对大家有所帮助。-Buttons control the digital tube display program. Including proteus simulation circuit. Function is achieved by the number of buttons to control different light, although the feature is simple, but using a chip select, latch, can be used as single-chip I/O expansion port through the chip select good example. Themselves are learning programming, we want to help.
Platform: | Size: 43008 | Author: 里尔 | Hits:
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