Welcome![Sign In][Sign Up]
Location:
Search - latch

Search list

[SCMCourseDesign_StepMotor

Description: 基于80x86CPU为核心控制器的具备基本I/O接口功能的硬件电路系统原理图设计、PCB电路设计和软件编程设计。基本I/O接口电路包括:锁存器、缓冲器、地址译码器、8255接口、8253接口、A/D(D/A)转换电路、串行接口电路等;软件功能要求完成基本I/O接口电路控制和串口通信功能调试。-Based on 80x86CPU as the core controller with the basic I/O interface function of the hardware circuit system schematic design, PCB circuit design and software programming. The basic I/O interface circuit includes: latch, buffer, address decoder, 8255 interface, 8253 interface, A/D (D/A) conversion circuit, serial interface circuit, etc . software function requirements to complete the basic I/O interface circuit control and serial communication function debugging.
Platform: | Size: 558080 | Author: 杨易 | Hits:

[Otherdatasheet

Description: 很实用的一款新片 高压侧驱动的IC 具有硬件保护功能 驱动的高压侧可以达到六百伏ir2110datasheet(The IR2110/IR2113 are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.)
Platform: | Size: 318464 | Author: 502225211 | Hits:

[assembly language8、交通灯

Description: //---定义IO口---// #define GPIO_DIG P0 //显示段码端口,74HC573锁存器; #define GPIO_PALCE P1 //数码管片选端口,74HC138译码器; #define GPIO_TRAFFIC P2 //交通灯端口; sbit RED10=P2^0; //上人行道红灯; sbit GREEN10=P2^1; //上人行道绿灯; sbit RED11=P2^2; //上机动车红灯; sbit YELLOW11=P2^3; //上机动车黄灯; sbit GREEN11=P2^4; //上机动车绿灯; sbit RED00=P3^0; //右人行道红灯; sbit GREEN00=P3^1; //右人行道绿灯; sbit RED01=P2^5; //右机动车红灯; sbit YELLOW01=P2^6; //右机动车黄灯; sbit GREEN01=P2^7; //右机动车绿灯;(/ define IO port --- // #define GPIO_DIG P0 // show segment code port, 74HC573 latch; #define GPIO_PALCE P1 // digital segment select port, 74HC138 decoder; #define GPIO_TRAFFIC P2 // traffic light port; Sbit RED10 = P2 ^ 0; // on the street red light; Sbit GREEN10 = P2 ^ 1; // on the sidewalk green light; Sbit RED11 = P2 ^ 2; // on the motor red light; Sbit YELLOW11 = P2 ^ 3; // on the motor vehicle yellow light; Sbit GREEN11 = P2 ^ 4; // on the green car; Sbit RED00 = P3 ^ 0; // right walkway red light; Sbit GREEN00 = P3 ^ 1; // right lane green light; Sbit RED01 = P2 ^ 5; // right motor red light; Sbit YELLOW01 = P2 ^ 6; // right motor vehicle yellow light; Sbit GREEN01 = P2 ^ 7; // right motor green light;)
Platform: | Size: 26624 | Author: 9956 | Hits:

[SCMP2

Description: LED显示,8位共阴极,用锁存器74Ls373进行段所存及为锁存。(LED display, 8 bit common cathode, with the latch 74Ls373, the section is stored and latched.)
Platform: | Size: 20480 | Author: 空心儿稻草人 | Hits:

[SCMnew_simulation

Description: 通过时钟使普通的IO口模拟UART串口通讯(Use Timer_A CCR1 hardware output modes and CCR0 SCCI data latch // to implement UART function @ 2400 baud. Software does not directly read and // write to RX and TX pins, instead proper use of output modes and SCCI data // latch are demonstrated. Use of these hardware features eliminates ISR // latency effects as hardware insures that output and input bit latching and // timing are perfectly synchronised with Timer_A regardless of other // software activity. In the Mainloop the UART function readies the UART to // receive one character and waits in LPM3 with all activity interrupt driven. // After a character has been received, the UART receive function forces exit // from LPM3 in the Mainloop which echo's back the received character. // ACLK = TACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO)
Platform: | Size: 26624 | Author: ASA2017 | Hits:

[Embeded-SCM Develop八路抢答器完整资料

Description: 八路抢答,各用一个抢答按钮; 设置一个控制开关,该开关由主持人控制;具有数据锁存和显示功能,抢答开始后若有选手按动抢答按钮,编号立即锁存,此外,要封锁输入电路,禁止其他选手抢答。(Eight road, each with one answer button; set a control switch, the switch is controlled by the moderator; has a data latch and display function, answer after the start if players press the answer button number immediately latched, in addition, to block the input circuit, the prohibition of other players answer.)
Platform: | Size: 27896832 | Author: edasky | Hits:

[TA6932_V1.1

Description: TA6932是一种LED(发光二极管显示器)驱动控制专用电路,内部集成有MCU数字接口、数据锁存器、LED 高压驱动。本产品性能优良,质量可靠。主要应用于多段位显示屏驱动。采用SOP32的封装形式。(TA6932 is a LED (light emitting diode display) drive control special circuit, which is integrated with a MCU digital interface. Data latch, LED high voltage drive. This product has excellent performance and reliable quality. Mainly used in the multi segment display driver. The packaging form of SOP32 is used.)
Platform: | Size: 603136 | Author: xpan | Hits:

[VHDL-FPGA-Verilog信号分析与处理——MATLAB语.part1

Description: ① Verilog的抽象级别 ② Verilog的模块化设计 ③ 如何给端口选择正确的数据类型 ④ Verilog语言中latch的产生 ⑤ 组合逻辑反馈环 ⑥ 阻塞赋值与非阻塞赋值的不同 ⑦ FPGA的灵魂状态机 ⑧ 代码风格的重要性((1) the abstract level of Verilog The modular design of Verilog How to select the correct data type for the port (4) the generation of latch in Verilog language Combinational logic feedback loop The blocking and nonblocking assignment assignment different The soul of state machine FPGA The importance of the code style)
Platform: | Size: 1457152 | Author: mmelody | Hits:

[OtherExp301

Description: 这是一个D锁存器完整文件,打开quartus2运行即可(This is a complete file of the D latch, open the quartus2 to run)
Platform: | Size: 7461888 | Author: 瓜皮233 | Hits:

[DocumentsDP5020-V2

Description: DP5020是LED显示面板设计的驱动IC,它内建的CMOS位移寄存器与锁存功能,可以将串行的输入数据转换成平行输出数据格式。(DP5020 is the driving IC of LED display panel design. It has built-in CMOS shift register and latch function, which can transform serial input data into parallel output data format.)
Platform: | Size: 378880 | Author: 伟大95 | Hits:

[Otherplj

Description: 使用vhdl语言原件例化设计数字频率计,并用6位7段数码管计数。模块包括:十进制计数器,6位10进制计数器,Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6-bit decimal counter, Reg24 latch, Fp frequency divider, Ctrl frequency controller, Disp dynamic display.)
Platform: | Size: 11264 | Author: 贵阳余文乐 | Hits:

[assembly languageVerilog源代码

Description: 多种基本功能的Verilog代码实现,包括多路选择器,二进制到BCD码转换,二进制到格雷码转换,7段译码器,8位数据锁存器,移位寄存器等等多种功能。(Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions.)
Platform: | Size: 18432 | Author: MMK1 | Hits:

[hardware designTexas Instruments

Description: Texas Instruments常用元件库 TI Analog Timer Circuit.IntLib TI Logic Flip-Flop.IntLib TI Logic Gate 1.IntLib TI Logic Gate 2.IntLib TI Logic Latch.IntLib TI Logic Switch.IntLib TI Power Mgt Voltage Reference.IntLib TI Power Mgt Voltage Regulator.IntLib Texas Instruments Footprints.PcbLib等等(Texas Instruments TI Analog Timer Circuit.IntLib TI Logic Flip-Flop.IntLib TI Logic Gate 1.IntLib TI Logic Gate 2.IntLib TI Logic Latch.IntLib TI Logic Switch.IntLib TI Power Mgt Voltage Reference.IntLib TI Power Mgt Voltage Regulator.IntLib Texas Instruments Footprints.PcbLib)
Platform: | Size: 18945024 | Author: blue sky1954 | Hits:
« 1 2 ... 13 14 15 16 17 18»

CodeBus www.codebus.net