Description: Specifications
1. Top module name :SS (File name : SS.v)
2. Input pins: CLK, RESET, IN_VALID, INPUT [6:0]
- 2 -
3. Output pins: OUT_VALID, OUTPUT [6:0]
4. Synchronous active high RESET is used, and no latch design is allowed.
5. All input signals will be changed at negative edge of clock. IN_VALID is high
when INPUT [6:0] is valid.
6. OUT_VALID will be high when OUTPUT is valid, and test pattern will compare
your output signals to the correct answer.
7. The valid output sequence must be continuous without any interruption.
8. Input delay and output delay are 0.5*clock period.
9. After synthesis, check the “SS.area” and “SS.timing” in the folder “Report”.
The area report is valid only when the slack in the end of SS.timing is
non-negative.
10. All outputs are sampled at negative clock edge.
11. The clock period is 5 ns.
12. The output loading is 0.05.
To Search:
File list (Check if you may need any files):
STUDENTS_SCORE
..............\01_RTL
..............\......\01_run.f
..............\......\09_clear_up
..............\......\DEADJOE
..............\......\INCA_libs
..............\......\.........\irun.lnx86.08.10.nc
..............\......\.........\...................\.ncrun.lock
..............\......\.........\...................\.ncv.lock
..............\......\.........\...................\bind.lst.lnx86
..............\......\.........\...................\cds.lib
..............\......\.........\...................\cdsrun.lib
..............\......\.........\...................\files.ts
..............\......\.........\...................\hdl.var
..............\......\.........\...................\hdlrun.var
..............\......\.........\...................\ncelab.args
..............\......\.........\...................\ncelab.env
..............\......\.........\...................\ncelab.hrd
..............\......\.........\...................\ncsim.args
..............\......\.........\...................\ncsim.env
..............\......\.........\...................\ncsim_restart.args
..............\......\.........\...................\ncsim_restart.env
..............\......\.........\...................\ncverilog.args
..............\......\.........\...................\ncvlog.args
..............\......\.........\...................\ncvlog.env
..............\......\.........\...................\ncvlog.files
..............\......\.........\...................\ncvlog.hrd
..............\......\.........\...................\temp
..............\......\.........\worklib
..............\......\.........\.......\.cdsvmod
..............\......\.........\.......\.inca.db.132.lnx86
..............\......\.........\.......\cdsinfo.tag
..............\......\.........\.......\inca.lnx86.132.pak
..............\......\ncverilog.log
..............\......\novas.rc
..............\......\nWaveLog
..............\......\........\novas.rc
..............\......\........\nWave.cmd
..............\......\........\nWave.cmd.bak
..............\......\........\pes.bat
..............\......\........\turbo.log
..............\......\PATTERN.v
..............\......\SS.fsdb
..............\......\SS.v
..............\......\TESTBED.v
..............\PATTERN.v
..............\TESTBED.v
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