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[Program doc] verilog_dpll_

Description: 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
Platform: | Size: 3072 | Author: 何柳 | Hits:

[Program doc] DPLL5

Description: 基于FPGA的DPLL的设计打包文件,有详细的描述文件-Design of FPGA-Based DPLL package files
Platform: | Size: 961536 | Author: henry | Hits:

[VHDL-FPGA-Verilog] NCO_sin

Description: 介绍了压控震荡器(VCO)的设计，压缩包里面有VHDL语言编写的代码，在仿真器上可以实现仿真结果，非常不错 -The VHDL code of VCO
Platform: | Size: 3072 | Author: 吴晓英 | Hits:

[SCM] dfefe.doc

Description: 该高频正弦信号发生器基于直接数字频率合成（DDS）和数字锁相环技术（DPLL），以微控制器（MCU）和现场可编程逻辑门阵列（FPGA）为核心，辅以必要的外围电路设计而成。系统主要由正弦信号发生、红外遥控、高速模数（A/D）－数模（D/A）转换、信号调制和后级处理等模块组成。-The high-frequency sinusoidal signal generator based on Direct Digital Synthesis (DDS) and digital PLL (DPLL), a microcontroller (MCU) and field programmable gate array (FPGA) as the core, supplemented by the necessary peripheral from circuit design. System is composed of sinusoidal signal, infrared remote control, high-speed module (A/D)- digital-analog (D/A) conversion, signal modulation and post-level processing modules.
Platform: | Size: 243712 | Author: henry | Hits:

[VHDL-FPGA-Verilog] xapp854

Description: Digital Phase-Locked Loop (DPLL) Reference Design
Platform: | Size: 574464 | Author: malijun | Hits:

[WEB Code] dpll

Description: 淘宝拍拍网店流量统计源码淘宝拍拍网店流量统计源码 -Taobao Shop pat pat traffic statistics source Taobao Taobao shop source traffic statistics traffic statistics source pat Shop
Platform: | Size: 70656 | Author: 明亮 | Hits:

[VHDL-FPGA-Verilog] vhdl3

Description: 介绍一种基于VHDL 语言的全数字锁相环实现方法，并用这种方法在FPGA 中实现了全数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demodulation of bit synchronization modules.
Platform: | Size: 230400 | Author: 枫蓝 | Hits:

[matlab] dpll_ieee

Description: implementation of dpll.a technique used by ieee.
Platform: | Size: 248832 | Author: bhargav | Hits:

[VHDL-FPGA-Verilog] mydesign_DPLL

Description: 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
Platform: | Size: 930816 | Author: 123456 | Hits:

[Program doc] DPLL

Description: 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
Platform: | Size: 798720 | Author: taotao | Hits:

[matlab] DPLL

Description: 模数转换的数字锁相环，代码中有详细的说明-digital phase lock loop
Platform: | Size: 2048 | Author: 张 | Hits:

[Communication] Untitled8

Description: source code and matlab code for second order dpll in digital signal processor
Platform: | Size: 1024 | Author: nithi | Hits:

[Communication-Mobile] bit-sychronization

Description: 全数字锁相环实现位同步，通过3个触发器实现码元的边沿提取。基带码采用M序列仿真。-DPLL to achieve bit synchronization, achieved through three trigger symbol of the edge extraction. Baseband codes using M-sequence simulation.
Platform: | Size: 569344 | Author: 林竹 | Hits:

[VHDL-FPGA-Verilog] digital_pll_cicc_tutorial_perrott

Description: Very good dpll tutorial.
Platform: | Size: 3821568 | Author: seek | Hits:

[VHDL-FPGA-Verilog] VHDL-FPGA-DLL

Description: 自动检测中英文中译英英译中百度翻译翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop DPLL VHDL realization-自动检测中英文中译英英译中百度翻译翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop DPLL VHDL realization
Platform: | Size: 230400 | Author: ldd | Hits:

[VHDL-FPGA-Verilog] VHDL-FPGA-ALL-digital-DDLL

Description: VHDL 全数字锁相环 ise7.1i环境实现内有代码和时域仿真结果-A VHDL language based on all digital phase-locked loop DPLL VHDL realization
Platform: | Size: 230400 | Author: ldd | Hits:

[matlab] DPLL

Description: 二阶锁相环仿真，输入频偏为阶跃信号时的仿真-pll simulation
Platform: | Size: 1024 | Author: 李宁 | Hits:

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[Program doc] verilog_dpll_

[Program doc] DPLL5

[VHDL-FPGA-Verilog] NCO_sin

[SCM] dfefe.doc

[VHDL-FPGA-Verilog] xapp854

[WEB Code] dpll

[VHDL-FPGA-Verilog] vhdl3

[matlab] dpll_ieee

[VHDL-FPGA-Verilog] mydesign_DPLL

[Program doc] DPLL

[matlab] DPLL

[Communication] Untitled8

[Communication-Mobile] bit-sychronization

[VHDL-FPGA-Verilog] digital_pll_cicc_tutorial_perrott

[VHDL-FPGA-Verilog] VHDL-FPGA-DLL

[VHDL-FPGA-Verilog] VHDL-FPGA-ALL-digital-DDLL

[matlab] DPLL

[VHDL-FPGA-Verilog] APDLL

[File Format] fm_txrx_simple

[matlab] PhasePLockedPLoop

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