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[Console] dpll界面程序

Description: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序，请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
Platform: | Size: 4081 | Author: zhangfj_99 | Hits:

[Develop Tools] 复件 数字锁相环程序

Description: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Platform: | Size: 121143 | Author: zhangfj_99 | Hits:

[Other resource] dll11254

Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
Platform: | Size: 19261 | Author: 刘仪 | Hits:

[Other resource] fdpll

Description: 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: | Size: 2037 | Author: 陈德炜 | Hits:

[Communication] dpll_4

Description: 实现4阶数字锁相环，老外写的，有详细注释，如果您觉得不错，就re一下-achieve four bands DPLL, a foreigner writing a detailed notes, if you think it's good, what re
Platform: | Size: 1981 | Author: liu | Hits:

[Other resource] verilogpll

Description: 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
Platform: | Size: 3821 | Author: letheo | Hits:

[Software Engineering] PLLprogram

Description: 数字锁相环程序，适合于FM、AM开发 数字锁相环程序，适合于FM、AM开发-DPLL procedures for FM, AM Development DPLL procedures for FM, AM Development
Platform: | Size: 31029 | Author: whuasan | Hits:

[OS Develop] PLLpro

Description: 关于数字锁相环的使用，结合FM,AM的使用来说明-DPLL on the use of combined FM and AM to illustrate the use of
Platform: | Size: 10670 | Author: whuayan | Hits:

[Other resource] 010919.pdf

Description: 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL description and achieve functional simulation, followed by graphic shows
Platform: | Size: 287252 | Author: 巢海步 | Hits:

[Communication-Mobile] pll_improvement

Description: 一种改进的全数字锁相环设计 一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
Platform: | Size: 102669 | Author: 李敏 | Hits:

[Other resource] VHDLDPLL

Description: 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
Platform: | Size: 168107 | Author: 李湘鲁 | Hits:

[WEB Code] zicaiyang

Description: 技术文章《自采样比例积分控制全数字锁相环的性能分析和实现》有一定参考价值-technical article, "Since sampling proportional integral control DPLL performance analysis and achieve" a certain reference value
Platform: | Size: 230052 | Author: 李湘鲁 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: dpll is used to lock the data
Platform: | Size: 1024 | Author: jkdgf | Hits:

[VHDL-FPGA-Verilog] Intelligent-modulus-DPLL-control-design-and-analys

Description: 智能模值控制的数字锁相环的FPGA设计与分析Intelligent modulus DPLL control design and analysis of FPGA-Intelligent modulus DPLL control design and analysis of FPGA
Platform: | Size: 261120 | Author: heart112 | Hits:

[VHDL-FPGA-Verilog] FPGA-based-design-of-DPLL

Description: 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
Platform: | Size: 416768 | Author: 阿啊 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 本工程为锁相环，采用全数字系统设计，输出频率在10M~100M之间！可改进。-This project is phase-locked loop, all-digital system design, the output frequency between the 10M ~ 100M! Can be improved.
Platform: | Size: 437248 | Author: 小吴 | Hits:

[hardware design] dpll

Description: 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods
Platform: | Size: 1024 | Author: 王铎皓 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)
Platform: | Size: 192512 | Author: CrazyICer | Hits:

[hardware design] dpll源程序

Description: 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the phase.)
Platform: | Size: 1024 | Author: 和风5254 | Hits:
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