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[Documents] verilogpll1234

Description: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Platform: | Size: 93479 | Author: li | Hits:

[Other resource] dpll0227

Description: DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
Platform: | Size: 272211 | Author: s | Hits:

[Other resource] chip1

Description: CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
Platform: | Size: 30562 | Author: sss | Hits:

[Other resource] dpll0226

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 184894 | Author: sss | Hits:

[Other resource] DPLL0227+V+qt6

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 279141 | Author: sss | Hits:

[Other resource] pll1218

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 109264 | Author: sss | Hits:

[Other resource] digital_loopback

Description: 基于ti公司6713dsp的数字锁相环，运行环境为ccs3.1。希望有所帮助。-ti-based company 6713dsp the DPLL, the operating environment for ccs3.1. Want some help.
Platform: | Size: 85128 | Author: 水歌 | Hits:

[Develop Tools] 060107[1].pdf

Description: 全数字锁相环,包括ＤＰＤ，ＤＬＦ，ＤＣＯ．-DPLL, including the DPD, DLF, the making.
Platform: | Size: 89078 | Author: 熊静 | Hits:

[Communication] all_digital_phase_locked_loop

Description: 一篇关于数字锁相环的很好的文章，费了很大力气才搞到的-a DPLL on the good paper, and a great effort will involve the
Platform: | Size: 249232 | Author: 刘小同 | Hits:

[Develop Tools] changyongmokuai

Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
Platform: | Size: 793855 | Author: 1 | Hits:

[Other resource] 5509aUSBAPLL

Description: 5509A usb模块由默认的DPLL转向AP-5509A module usb default by the DPLL to AP
Platform: | Size: 1414 | Author: pp | Hits:

[Other resource] 200761311574149479

Description: 介绍了如何使用数字锁相环,如何用VHDL实现数字锁相环-on how to use the DPLL, how to use VHDL DPLL
Platform: | Size: 63234 | Author: zhaojia | Hits:

[Software Engineering] DPLL

Description: 介绍了一宽带的数字锁相环的实现方法，欢迎大家踊跃下载
Platform: | Size: 1109954 | Author: 皱接 | Hits:

[Applications] dpll

Description: 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，
Platform: | Size: 1414 | Author: lily | Hits:

[Other resource] dpll

Description: ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ
Platform: | Size: 4731 | Author: YP | Hits:

[Other resource] FPGA-DPLL

Description: 基于FPGA实现的一种新型数字锁相环
Platform: | Size: 181403 | Author: lixu | Hits:

[source in ebook] 数字锁相环

Description: DPLL
Platform: | Size: 1242 | Author: hxy687 | Hits:

[SourceCode] verilog dpll（数字锁相环）

Description: 用xilinx ise 10.1实现了数字锁相环，仅供参考
Platform: | Size: 667591 | Author: ronglijun@gmail.com | Hits:

[VHDL-FPGA-Verilog] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Platform: | Size: 111616 | Author: 孙犁 | Hits:
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