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[Software Engineering] pll

Description: 数字锁相环教案。数字锁相环教案。-DPLL lesson plans. DPLL lesson plans.
Platform: | Size: 152576 | Author: wang sheng | Hits:

[VHDL-FPGA-Verilog] FPGA-DPLL

Description: 基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
Platform: | Size: 181248 | Author: lixu | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[DSP program] 5509A_USB_APLL_TO_DPLL

Description: This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-locked loop (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.-This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Exampleassembly programs for programming and switching to and from the APLL are alsoprovided in the attached zip file. It is assumed that the reader is familiar with the useand operation of the C5506/C5507/C5509A USB digital phase-locked loop (DPLL) andC55x
Platform: | Size: 5120 | Author: han | Hits:

[DSP program] 5509A_USB_DPLL_TO_APLL

Description: The TMS320VC5506/C5507/C5509A USB peripherals can be clocked from either the USB APLL or the USB DPLL. Since the APLL is inherently more noise tolerant and has less long-term jitter than the DPLL, it is recommended that you switch to it for any USB operations.-The TMS320VC5506/C5507/C5509A USB peripherals can be clocked from either the USB APLL or theUSB DPLL. Since the APLL is inherently more noise tolerant and has less long-term jitter than the DPLL, it is recommended that you switch to it for any USB operations.
Platform: | Size: 5120 | Author: han | Hits:

[matlab] 11112323

Description: 基于锁相环Top-down的建模方法在MATLAB环境下建立数字锁相环完整的仿真模型，并用SIMULINK对数字锁相环的仿真模型进行仿真。　-Top-down phase-locked loop based on the modeling method in MATLAB environment DPLL set up a complete simulation model, and use of digital phase-locked loop SIMULINK simulation model simulation.
Platform: | Size: 198656 | Author: 王利华 | Hits:

[Other] ASurveyofDigitalPhaseLockedloops

Description: 这篇文章的目的是，提出在1960年到1980年期间，对在数字锁相环(DPLL)的领域内完成的理论/试验著作的有系统的调查。数字锁相环描述在前后一致的通讯和跟踪接收机的实施(数字化)过程中需要的组成部分的核心-The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL’s) during the period of 1960 to 1980.The DPLL represents the heart of the building blocks required in the implementation of coherent (In digital) communications and tracking receivers
Platform: | Size: 1295360 | Author: 李帅 | Hits:

[VHDL-FPGA-Verilog] shuzisuoxiang

Description: 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of applications. With the traditional analog circuit implementation of the PLL in comparison, DPLL with high accuracy, free from the impact of temperature and voltage, loop bandwidth and center frequency adjustable programming, easy to build a high-order phase-locked loop, etc..
Platform: | Size: 1024 | Author: hellen | Hits:

[VHDL-FPGA-Verilog] FPGAphaselockedloopdesign

Description: 介绍了应用VHDL技术设计嵌入式全数字锁相环路的方法，详细叙述了其工作原理和设计思想，并用可编程逻辑器件FPGA实现。-Introduce the application of VHDL technical design embedded DPLL road approach, described in detail its working principle and design idea, and programmable logic device FPGA implementation.
Platform: | Size: 286720 | Author: 朱雯 | Hits:

[Other] dpll

Description: 锁相环的基本原理，设计结构，及实现过程介绍-The basic principles of phase-locked loop, design structure, and the realization of the process of introducing
Platform: | Size: 1664000 | Author: 张兆伟 | Hits:

[Communication-Mobile] dco

Description: dpll的一个中间器件，实现增量-减量DCO功能-dpll of an intermediate device to achieve incremental- DCO function reduction
Platform: | Size: 2048 | Author: 小小 | Hits:

[Other] DPLL

Description: pll 的数字实现大家支持第一次传-pll digital impliment
Platform: | Size: 49152 | Author: zhangfuquan | Hits:

[Communication-Mobile] dpll

Description: All Digital Phase-Locked Loop verilog source code
Platform: | Size: 1024 | Author: 李浩 | Hits:

[Modem program] all_digital_fm_receiver_latest

Description: Fm receiver using DP-Fm receiver using DPLL
Platform: | Size: 112640 | Author: sai | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[VHDL-FPGA-Verilog] pll

Description: DPLL由鉴相器、模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, synchronous detection circuit established, constitute a model N divider. The whole system of the center frequency (ie signal_in and signal_out the code rate of 2 times) to clk/8/N. modulus K K value addition and subtraction counter DPLL decision to establish the accuracy and synchronization time, K is larger, the simultaneous establishment of a long time, synchronization accuracy. contrary is short and low.
Platform: | Size: 1024 | Author: 鬼舞十七 | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve
Platform: | Size: 539648 | Author: sunnyhp | Hits:

[DSP program] dpll

Description: Digital Phase Locked Loop M-File
Platform: | Size: 1024 | Author: bumclouds2 | Hits:

[matlab] dpll_m

Description: DPLL implementation in matlab
Platform: | Size: 1024 | Author: p2p001 | Hits:

[VHDL-FPGA-Verilog] AD-PLL

Description: 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
Platform: | Size: 2048 | Author: yzn8625 | Hits:

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[Software Engineering] pll

[VHDL-FPGA-Verilog] FPGA-DPLL

[VHDL-FPGA-Verilog] DPLL(VHDL)

[DSP program] 5509A_USB_APLL_TO_DPLL

[DSP program] 5509A_USB_DPLL_TO_APLL

[matlab] 11112323

[Other] ASurveyofDigitalPhaseLockedloops

[VHDL-FPGA-Verilog] shuzisuoxiang

[VHDL-FPGA-Verilog] FPGAphaselockedloopdesign

[Other] dpll

[Communication-Mobile] dco

[Other] DPLL

[Communication-Mobile] dpll

[Modem program] all_digital_fm_receiver_latest

[VHDL-FPGA-Verilog] DPLL

[VHDL-FPGA-Verilog] pll

[VHDL-FPGA-Verilog] DPLL

[DSP program] dpll

[matlab] dpll_m

[VHDL-FPGA-Verilog] AD-PLL

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