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Description: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序,请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
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Description: 数字锁相环程序,适合于FM、AM开发
数字锁相环程序,适合于FM、AM开发-DPLL procedures for FM, AM Development DPLL procedures for FM, AM Development
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Size: 30720 |
Author: whuasan |
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Description: 关于数字锁相环的使用,结合FM,AM的使用来说明-DPLL on the use of combined FM and AM to illustrate the use of
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Size: 10240 |
Author: whuayan |
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Description: verilog ADPLL file with testbench.v
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Size: 25600 |
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Description: 技术文章《自采样比例积分控制全数字锁相环的性能分析和实现》有一定参考价值-technical article, "Since sampling proportional integral control DPLL performance analysis and achieve" a certain reference value
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Size: 229376 |
Author: 李湘鲁 |
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Description: intel 8088 架构的verilog代码,可以综合下载,在fpga上实现8088调试。-intel 8088 verilog structure of the code can be integrated download, fpga achieved in 8088 debugging.
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Size: 240640 |
Author: blueli |
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Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
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Size: 108544 |
Author: sss |
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Description: 频带数字通信中,频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
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Size: 8192 |
Author: rossi |
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Description: 5509A usb模块由默认的DPLL转向AP-5509A module usb default by the DPLL to AP
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Size: 1024 |
Author: pp |
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Description: 介绍了如何使用数字锁相环,如何用VHDL实现数字锁相环-on how to use the DPLL, how to use VHDL DPLL
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Size: 62464 |
Author: zhaojia |
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Description: 一个实现简单的数字锁相环Verilog代码,本人借鉴网上现有的代码后经修改在Cyclone II上调通实现,里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
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Size: 67584 |
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Description: 数字锁相环mb1504驱动程序和应用图纸-DPLL mb1504 driver and application drawings
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Size: 257024 |
Author: peishixiong |
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Description: 一个初步的数字锁相环程序,没有测试文件,应该可以运行。-DPLL an initial procedure, there is no test file should be able to run.
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Size: 1024 |
Author: 安刚 |
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Description: 数字锁相环控制产生信号程序详解以及控制字计算方法-DPLL Detailed procedures for the control signal and the control method of calculating the word
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Size: 3072 |
Author: 老白 |
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Description: 基于vhdl语言描述的dpll,以及图片-Based on the VHDL language is described dpll, as well as the picture
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Size: 5120 |
Author: wb |
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Description: 使用VHDL语言进行设计DPLL(数字锁相环)的相关文件-The use of VHDL language design DPLL (digital phase-locked loop) of the relevant documents
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Size: 223232 |
Author: 国家 |
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Description: 介绍了一种采用N 先于M 环路滤波器的全数字锁相环的设计实现。这种全数字锁
相环采用了N 先于M 环路滤波器,可以达到滤除噪声干扰的目的。文中讲述了这种全数字锁相环的结构和工作原理,提出了各单元电路的设计和实现方法,并给出了关键部件的VHDI 代码,最后用FPGA 予以实现。-A good reference for The Design and Realization of a Kind of DPLL Using
a N before M Loop FiIter
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Size: 226304 |
Author: Reguse |
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Description: 全数字锁相环(adpll)的部分源程序代码,是其中最重要的部分。-All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
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Size: 2048 |
Author: 林飞 |
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Description: 一个实现任意倍频的,输入参考频率未知的pll,已综合实现-frequency multiple rely on dpll,unknown reference input clock
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Size: 4096 |
Author: 刘彻 |
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Description: C语言实现了数字锁相环的程序,不过程序比较复杂,得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
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Size: 24576 |
Author: 蔡科 |
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