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Description: 简单的可配置dpll的VHDL代码。
用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
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Size: 2048 |
Author: 陈德炜 |
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Description: 实现4阶数字锁相环，老外写的，有详细注释，如果您觉得不错，就re一下-achieve four bands DPLL, a foreigner writing a detailed notes, if you think it's good, what re
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Size: 2048 |
Author: liu |
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Description: 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
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Size: 3072 |
Author: letheo |
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Description: 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL description and achieve functional simulation, followed by graphic shows
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Size: 286720 |
Author: 巢海步 |
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Description: 一种改进的全数字锁相环设计
一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
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Size: 102400 |
Author: 李敏 |
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Description: 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
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Size: 167936 |
Author: 李湘鲁 |
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Description: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
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Size: 93184 |
Author: li |
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Description: DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
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Size: 272384 |
Author: s |
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Description: CPLD的程序,分频,微分等,应用于DPLL
-CPLD procedures, frequency, differential, etc. can be applied to DPLL
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Size: 30720 |
Author: sss |
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Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
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Size: 184320 |
Author: sss |
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Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
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Size: 278528 |
Author: sss |
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Description: 基于ti公司6713dsp的数字锁相环，运行环境为ccs3.1。希望有所帮助。-ti-based company 6713dsp the DPLL, the operating environment for ccs3.1. Want some help.
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Size: 126976 |
Author: 水歌 |
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Description: 全数字锁相环,包括ＤＰＤ，ＤＬＦ，ＤＣＯ．-DPLL, including the DPD, DLF, the making.
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Size: 89088 |
Author: 熊静 |
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Description: 一篇关于数字锁相环的很好的文章，费了很大力气才搞到的-a DPLL on the good paper, and a great effort will involve the
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Size: 248832 |
Author: 刘小同 |
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Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
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Size: 793600 |
Author: 1 |
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Description: 介绍了一宽带的数字锁相环的实现方法，欢迎大家踊跃下载 -Introduction of a broadband digital phase-locked loop method, enthusiastically welcomed the U.S. Download
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Size: 1110016 |
Author: 皱接 |
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Description: 数字锁相环实现源码，有很大的参考价值。
由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.-DPLL realize source, has a great reference value. By the phase detector counter modulus K addition and subtraction circuit synchronous pulse addition and subtraction to establish surveillance mode N divider circuit constituted.
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Size: 2048 |
Author: sharny |
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Description: 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
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Size: 1024 |
Author: lily |
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Description: 本文在说明全数字锁相环的基础上，提出了一种利用FPGA设计一阶全数字锁相环的方法，并
给出了关键部件的RTL可综合代码，并结合本设计的一些仿真波形详细描述了数字锁相环的工作过程，最后对一些有关的问题进行了讨论。-In this paper, that all-digital phase-locked loop based on a FPGA design using first-order DPLL method, and gives the key components of the RTL code can be integrated and combined with the design of some of the detailed simulation waveform describes the working process of digital phase-locked loop, the last of some related issues were discussed.
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Size: 286720 |
Author: wangyunshann |
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Description: 一阶全数字锁相环VERLOGIC程序代码，调试通过。-First-order DPLL VERLOGIC program code, debugging through.
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Size: 2048 |
Author: 梁大法 |
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