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Description: OMAP2-specific DPLL control functions.
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Size: 2048 |
Author: moliezw |
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Description: OMAP2 3 4 DPLL clock functions.
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Size: 4096 |
Author: guwouht |
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Description: enable DPLL autoidle bits.
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Size: 3072 |
Author: sekgviu |
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Description: Lock USB DPLL on OMAP4 devices so that the L3INIT power domain can transition to retention state when not in use.
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Size: 14336 |
Author: yodeihei |
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Description: 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, digital locks, four have signed division synchronous FIFO, DPLL design and Cordic algorithm. For beginners VHDL great reference value.
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Size: 20480 |
Author: 朱召宇 |
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Description: DPLL rate rounding: minimum DPLL multiplier, divider values.
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Size: 5120 |
Author: tengjevs |
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Description: Finalizes DPLL registration process. In case a failure (clk-ref or clk-bypass is missing), the clock is added to retry list and the initialization is retried on later stage.
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Size: 15360 |
Author: menlangmv |
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Description: CM_CLKEN_PLL.EN bit values - not all are available for every DPLL.
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Size: 4096 |
Author: peitwwao |
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Description: experimental fullduplex mode with DPLL BRG for MODEMs without clock recovery.
-experimental fullduplex mode with DPLL BRG for MODEMs without clock recovery.
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Size: 2048 |
Author: yengwstb |
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Description: 一个全数字锁相环，可用于信号的复用中，进行调制和借条操作。-A digital phase-locked loop can be used to signal multiplexing, modulation and IOU operations.
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Size: 10240 |
Author: 郝建华 |
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Description: a simulink model for DPLL with NCO
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Size: 24576 |
Author: dotmcontrol |
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Description: 对输入信号实现1.5倍频，输入数字信号频率范围 是1050~1100Hz（不一定是50 占空比的方波，并且输入信号频率可能在1050~1100Hz内缓慢变化，频率变化速率不高于小于10Hz/s），要求输出50 占空比的信号，并且频率是输入的1. 5倍，并能够连续跟踪输入频率的以及相位改变。-The input signal to achieve the 1.5 multiplier, input digital signal frequency range is 1050 ~ 1100Hz (not necessarily a 50 duty cycle square wave, and the input signal frequency may change slowly in 1050 ~ 1100Hz, frequency change rate is not higher than the less than 10Hz/s), the requirements of 50 duty cycle output signal, and the frequency is 1.5 times the input voltage, and continuously track the input frequency, and phase change.
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Size: 4096 |
Author: 刘东辉 |
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Description: matlab代码：计算数字锁相环中数字滤波器的参数，满足稳定性和环路带宽要求。-matlab code: calculate the parameters of DLF in DPLL to meet the specific loop bandwidth and stability.
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Size: 2048 |
Author: Leozhang |
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Description: 通过串口uart rs232控制的全数字锁相环，dpll，
可锁时钟相位-UART CTORLER DPLL MODULE CLK
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Size: 33792 |
Author: |
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Description: simulation of a digital pll for power system
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Size: 11264 |
Author: saeed |
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Description: simulation ofa dpll fixed point for single phase system
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Size: 11264 |
Author: saeed |
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Description: UPS锁相环Matlab/simulink仿真(dpll Matlab/simulink)
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Size: 176128 |
Author: 小线圈
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Description: 基于matlab的数字pll实现，鉴相器，滤波器以及压控震荡器组成，具备良好的锁相功能，适合入门学习(Digital PLL based on MATLAB, phase detector, filter and voltage controlled oscillator, phase lock function has good, suitable for beginners to learn)
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Size: 17408 |
Author: qiya2 |
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Description: 介绍了一种基于DSP 的高频感应加热电源。现以MOSFET为开关器件，并通过逆变器并联扩容为60kW/300kHz。采用多重斩波技术，增大了斩波电路的容量，将基于DSP 的fuzzy-DPLL 复合数字锁相环技术应用在高频场合，使锁相有快速的动态性能和高精度的稳态性能，实现了对负载频率的可靠跟踪及对逆变状态的可靠控制，提高了逆变器
的工作效率和功率因数。(A high frequency induction heating power supply based on DSP. MOSFET is now used as a switch device, and the capacity of 60kW/300kHz is expanded in parallel through the inverter.Using multiple chopping technology, the capacity of chopper circuit is increased, and the fuzzy-DPLL composite digital phase locked loop technology based on DSP is applied to the high frequency situation, so that the lock is locked.It has fast dynamic performance and high precision steady state performance. It achieves reliable tracking of load frequency and reliable control of inverter state, and improves inverter.Working efficiency and power factor.)
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Size: 751616 |
Author: destyni |
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