- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 4kb
- Update:
- 2015-11-02
- Downloads:
- 0 Times
- Uploaded by:
- 刘东辉
Description: The input signal to achieve the 1.5 multiplier, input digital signal frequency range is 1050 ~ 1100Hz (not necessarily a 50 duty cycle square wave, and the input signal frequency may change slowly in 1050 ~ 1100Hz, frequency change rate is not higher than the less than 10Hz/s), the requirements of 50 duty cycle output signal, and the frequency is 1.5 times the input voltage, and continuously track the input frequency, and phase change.
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DPLL\Ctrl.vhd
....\dpll_tb.ucf
....\dpll_tb.vhd
DPLL
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