- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 20kb
- Update:
- 2015-05-18
- Downloads:
- 0 Times
- Uploaded by:
- 朱召宇
Description: The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, digital locks, four have signed division synchronous FIFO, DPLL design and Cordic algorithm. For beginners VHDL great reference value.
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code\实验一\avoidShake.vhd
....\......\freqDivider.vhd
....\......\segment7.vhd
....\......\serialDetecct.ucf
....\......\serialDetecct.vhd
....\....七\exp0702.ucf
....\......\exp0702.vhd
....\....三\code.ucf
....\......\Code.vhd
....\....二\avoidShake.vhd
....\......\code.ucf
....\......\Code.vhd
....\......\counter.vhd
....\......\freqDivider.vhd
....\......\segment7.vhd
....\....六\DPLL .vhd
....\......\dpll_tb .ucf
....\......\dpll_tb .vhd
....\....四\Ram_FIFO.vhd
....\......\TestBenchFile.vhd
....\实验一
....\实验七
....\实验三
....\实验二
....\实验六
....\实验四
code
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