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[VHDL-FPGA-Verilog] FdplllzipP

Description: ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware description council meeting Verilog HDL top-level file DPLL is. V
Platform: | Size: 5120 | Author: 陪同 | Hits:

[VHDL-FPGA-Verilog] sfdppllli

Description: 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.
Platform: | Size: 2048 | Author: 房产 | Hits:

[VHDL-FPGA-Verilog] 759744

Description: dpll源代码，实现基本功能，具体BUG需自己修改-dpll unit
Platform: | Size: 124928 | Author: taoyuan | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 90度锁定的数字锁相环的设计的VHDL源代码-The VHDL code of Digital Phase-Locked Loop Based on CPLD
Platform: | Size: 350208 | Author: sunjinqiu | Hits:

[Software Engineering] USB1.1-VHDL

Description: USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.-USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.
Platform: | Size: 6144 | Author: LJ | Hits:

[matlab] dpll

Description: Simulink all digital p-Simulink all digital plll
Platform: | Size: 11264 | Author: falamash | Hits:

[Other] ver3

Description: 全数字锁相环的verilog代码，希望能有帮助-The DPLL verilog code, hoping to help! ! !
Platform: | Size: 956416 | Author: 解超 | Hits:

[Software Engineering] Matlab-about-pll

Description: 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全 数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable to all-digital phase-locked loop DPLL layout SPICE simulation, with the The model simulation results verified.
Platform: | Size: 259072 | Author: dashu | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
Platform: | Size: 1024 | Author: wangxin | Hits:

[Linux-Unix] clkt2xxx_dpll

Description: OMAP2-specific DPLL control functions driver
Platform: | Size: 1024 | Author: vunvoqun | Hits:

[Linux-Unix] dpll44xx

Description: OMAP4-specific DPLL control functions driver for Linux.
Platform: | Size: 1024 | Author: peixouliu | Hits:

[Linux-Unix] dpll3xxx

Description: OMAP3/4 - specific DPLL control functions
Platform: | Size: 4096 | Author: nierajui | Hits:

[Linux-Unix] clkt2xxx_dpllcore

Description: DPLL + CORE_CLK composite clock functions
Platform: | Size: 2048 | Author: kosancang | Hits:

[VHDL-FPGA-Verilog] verilog-pll

Description: 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
Platform: | Size: 1323008 | Author: loadziliao | Hits:

[VHDL-FPGA-Verilog] dpll2

Description: 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
Platform: | Size: 1024 | Author: 朱小波 | Hits:

[Other] Principles-and-Applications-of-DPLL

Description: 《数字锁相环路原理与应用》/胡华春.石玉编著.1990.上海科学技术出版社-Principles and Applications of digital phase locked loop
Platform: | Size: 2786304 | Author: 程硕 | Hits:

[File Format] ADPLL-patent

Description: 全数字锁相环的几个专利，全部为英文，很好的参考资料-DPLL patent
Platform: | Size: 411648 | Author: 程硕 | Hits:

[File Format] 00258213

Description: This paper presents a generalized nonlinear (Markov) analysis technique for evaluation of the statistical performance of uniformly sampled digital phase-locked loops (DPLL). Recently proposed synchronization algorithms use more discrete time signal processing due to the advances in integrated circuit fabrication (i.e., gate arrays and ROMs).-This paper presents a generalized nonlinear (Markov) analysis technique for evaluation of the statistical performance of uniformly sampled digital phase-locked loops (DPLL). Recently proposed synchronization algorithms use more discrete time signal processing due to the advances in integrated circuit fabrication (i.e., gate arrays and ROMs).
Platform: | Size: 440320 | Author: lala | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
Platform: | Size: 6144 | Author: chi zhang | Hits:

[Linux-Unix] dpll44xx

Description: OMAP4-specific DPLL control functions for Linux v2.13.6.
Platform: | Size: 2048 | Author: bunraxong | Hits:
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