Description: Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
- [verilogpll1234] - verilog DPLL the design, verilog based o
- [dpll_demo] - A simple digital PLL Verilog code, I dra
- [E1_DCR] - 2MHz data clock recovery circuit, includ
- [PD_using_FPGA] - Verilog preparation phase of the FPGA-ba
- [DigitalPLL] - Introduce the basic structure of digital
- [pll_verilog_code] - This is a period of pll verilog code, ye
- [pll] - Implementation of the principle of phase
- [DPLL] - DPLL
- [PLLfpgapaper] - Paper digital PLL, FPGA implementation f
- [dpll_m] - DPLL implementation in matlab
File list (Check if you may need any files):
dpll\db\dpd.asm.qmsg
....\..\dpd.cbx.xml
....\..\dpd.cmp.bpm
....\..\dpd.cmp.cdb
....\..\dpd.cmp.ecobp
....\..\dpd.cmp.hdb
....\..\dpd.cmp.logdb
....\..\dpd.cmp.rdb
....\..\dpd.cmp.tdb
....\..\dpd.cmp0.ddb
....\..\dpd.db_info
....\..\dpd.eco.cdb
....\..\dpd.eda.qmsg
....\..\dpd.fit.qmsg
....\..\dpd.hier_info
....\..\dpd.hif
....\..\dpd.map.bpm
....\..\dpd.map.cdb
....\..\dpd.map.ecobp
....\..\dpd.map.hdb
....\..\dpd.map.logdb
....\..\dpd.map.qmsg
....\..\dpd.map_bb.cdb
....\..\dpd.map_bb.hdb
....\..\dpd.map_bb.hdbx
....\..\dpd.map_bb.logdb
....\..\dpd.pre_map.cdb
....\..\dpd.pre_map.hdb
....\..\dpd.psp
....\..\dpd.root_partition.cmp.atm
....\..\dpd.root_partition.cmp.dfp
....\..\dpd.root_partition.cmp.hdbx
....\..\dpd.root_partition.cmp.logdb
....\..\dpd.root_partition.cmp.rcf
....\..\dpd.root_partition.map.atm
....\..\dpd.root_partition.map.hdbx
....\..\dpd.root_partition.map.info
....\..\dpd.rtlv.hdb
....\..\dpd.rtlv_sg.cdb
....\..\dpd.rtlv_sg_swap.cdb
....\..\dpd.sgdiff.cdb
....\..\dpd.sgdiff.hdb
....\..\dpd.signalprobe.cdb
....\..\dpd.sld_design_entry.sci
....\..\dpd.sld_design_entry_dsc.sci
....\..\dpd.syn_hier_info
....\..\dpd.tan.qmsg
....\..\dpd.tis_db_list.ddb
....\..\prev_cmp_dpd.asm.qmsg
....\..\prev_cmp_dpd.eda.qmsg
....\..\prev_cmp_dpd.fit.qmsg
....\..\prev_cmp_dpd.map.qmsg
....\..\prev_cmp_dpd.qmsg
....\..\prev_cmp_dpd.tan.qmsg
....\dlf.v
....\dlf.v.bak
....\doc.v
....\doc.v.bak
....\dpd.asm.rpt
....\dpd.done
....\dpd.eda.rpt
....\dpd.fit.rpt
....\dpd.fit.smsg
....\dpd.fit.summary
....\dpd.flow.rpt
....\dpd.map.rpt
....\dpd.map.smsg
....\dpd.map.summary
....\dpd.pin
....\dpd.pof
....\dpd.qpf
....\dpd.qsf
....\dpd.qws
....\dpd.sof
....\dpd.tan.rpt
....\dpd.tan.summary
....\dpd.v
....\dpd.v.bak
....\dpll.v
....\dpll.v.bak
....\simulation\modelsim\cyclone_atoms.v
....\..........\........\dpd.cr.mti
....\..........\........\dpd.mpf
....\..........\........\dpd.sft
....\..........\........\dpd.vo
....\..........\........\dpd_modelsim.xrf
....\..........\........\dpd_v.sdo
....\..........\........\top.v
....\..........\........\vsim.wlf
....\..........\........\work\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e\verilog.asm
....\..........\........\....\................................\_primary.dat
....\..........\........\....\................................\_primary.vhd
....\..........\........\....\cyclone_and1\verilog.asm
....\..........\........\....\............\_primary.dat
....\..........\........\....\............\_primary.vhd
....\..........\........\....\............6\verilog.asm
....\..........\........\....\.............\_primary.dat
....\..........\........\....\.............\_primary.vhd
....\..........\........\....\.........smiblock\verilog.asm
....\..........\........\....\.................\_primary.dat
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