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Description: Verilog HDL数字设计与综合 夏宇闻译（第二版）-Verilog HDL digital design and synthesis Xia Wen translation (second edition)
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Size: 538624 |
Author: 杨轶帆 |
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Description: 从算法设计到硬线逻辑的实现
Verilog HDL牛人编写的有关经典书籍，其中包含很多例子-From algorithm design to hard-line Verilog HDL logic realize cattle were prepared by the classic book, which contains many examples
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Size: 830464 |
Author: 杨轶帆 |
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Description: Verilog HDL Guide,是学习Verilog不错的教程,是CHM格式的-Verilog HDL Guide, is a good tutorial to learn Verilog is the CHM format
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Size: 1723392 |
Author: 李成有 |
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Description: HDL开发毕业论文，HDL在FPGA上的应用-HDL Development Thesis, HDL in the FPGA application
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Size: 1008640 |
Author: 玄天 |
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Description: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
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Size: 12288 |
Author: maliang |
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Description: 王金明：《Verilog HDL 程序设计教程》程序 把程序部分单独列出来 让你跳过大段文字直接接触源程序 -Wang Jinming:
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Size: 175104 |
Author: 唐星 |
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Description: 简易数字频率计，用Verilog HDL编写的，基于Quartus II实现，结构清晰，功能较为全面，能满足简单的频率测量要求-Simple digital frequency meter, using Verilog HDL prepared, based on the Quartus II realize, clear structure, function is more comprehensive to meet the simple requirements of frequency measurement
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Size: 404480 |
Author: 余翔 |
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Description: iic slave verilog hdl code
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Size: 1024 |
Author: hrui |
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Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
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Size: 180224 |
Author: panyouyu |
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Description: Verilog HDL Synthesis, A Practical Primer
学习Verilog HDL一本很不错的英文书，比较透彻-Verilog HDL Synthesis, A Practical Primer learning Verilog HDL a very good English books, more thorough
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Size: 4994048 |
Author: 文字 |
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Description: verilog HDL 基础实验源码，比较实用-verilog HDL experimental basis for source code, more practical
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Size: 1006592 |
Author: mosquito |
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Description: verilog HDL综合实验源代码，比较实用-Comprehensive Experiment verilog HDL source code, more practical
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Size: 543744 |
Author: mosquito |
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Description: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
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Size: 2048 |
Author: 吴俊泉 |
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Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
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Size: 2048 |
Author: 张诚 |
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Description: 第一章 数字信号处理、计算、程序、算法和硬线逻辑的基本概念
第二章 Verilog HDL设计方法概述
第三章 Verilog HDL的基本语法
第四章 不同抽象级别的Verilog HDL模型
第五章 基本运算逻辑和它们的Verilog HDL模型
第六章 运算和数据流动控制逻辑
第七章 有限状态机和可综合风格的Verilog HDL-The first chapter of digital signal processing, computing, procedures, algorithms and hard-wired logic of the basic concepts of Chapter II Verilog HDL design methods outlined in Chapter III of the basic Verilog HDL syntax in Chapter IV of different abstraction levels of Verilog HDL model of Chapter V of the basic arithmetic logic and Verilog HDL model of their Chapter VI computing and data flow control logic of Chapter VII of the finite state machine and an integrated style of Verilog HDL
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Size: 1079296 |
Author: 碗筷 |
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Description: VerilogHDL_advanced_digital_design_code_Ch6
Verilog HDL 高级数字设计源码ch6-Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch6Verilog HDL source CH6
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Size: 69632 |
Author: lianlianmao |
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Description: Generic FIFO, writen in verilog hdl
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Size: 12288 |
Author: marco |
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Description: Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples and has made it clear that it is rare to learn Verilog good information.
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Size: 1887232 |
Author: ZY |
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Description: 32位除法器
被除数和除数均为16位整数，16位小数
商为32位整数，16位小数
余数为16位整数，16位小数
Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
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Size: 1024 |
Author: 李春阳 |
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Description: 基于Verilog HDL设计的多功能数字钟，有兴趣的-Verilog HDL-based design of multi-function digital clock, interested
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Size: 38912 |
Author: 沈三思 |
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