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[VHDL-FPGA-Verilog] verilog SDRAM core

Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
Platform: | Size: 27648 | Author: 于飞 | Hits:

[Books] VerilogBook

Description: Verilog HDL硬件描述语言的教程-Verilog HDL Hardware Description Language Guide
Platform: | Size: 143360 | Author: 田正 | Hits:

[SCM] Verilog HDL练习题

Description: 硬件描述语言，对学习EDA的人，特别是初学者都有很大的参考价值。-hardware description language, to learn the EDA people, especially beginners have great reference value.
Platform: | Size: 78848 | Author: 陈盛 | Hits:

[Other] cpu的VERILOG描述

Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Platform: | Size: 369664 | Author: 陈俊 | Hits:

[VHDL-FPGA-Verilog] verilog hdl教程135例

Description: 浅显易懂的vrilogHDL的程序，可以帮助你迅速上手-Easy and simple VerilogHDL programs to help you to get to the language quickly.
Platform: | Size: 158720 | Author: 陈浩东 | Hits:

[source in ebook] SystemC片上系统设计源代码

Description: SystemC片上系统设计的源代码： 书籍介绍： SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。 本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。 本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
Platform: | Size: 2640896 | Author: c.li | Hits:

[VHDL-FPGA-Verilog] alu_vlog

Description: 学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
Platform: | Size: 154624 | Author: yiyi | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: Verilog HDL程序，对硬件开发有兴趣或需要的朋友赶快down下来-Verilog HDL procedures, the development of hardware are interested or needs a friend to see down quickly down
Platform: | Size: 37888 | Author: 石海潜 | Hits:

[VHDL-FPGA-Verilog] RISC8.ZIP

Description: 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
Platform: | Size: 80896 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] 双路脉冲发生器（veralog）

Description: Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is written I hope to help you, it can be mail : shaojunwu1@163.com
Platform: | Size: 4096 | Author: 邵君武 | Hits:

[VHDL-FPGA-Verilog] 用cpld实现曼彻斯特编码

Description: 用cpld实现曼彻斯特编码 用verilog HDL进行曼彻斯特编码，用于通信中-cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
Platform: | Size: 4096 | Author: 李鹏 | Hits:

[Game Program] HDLDumpCmd

Description: PS2游戏硬盘直灌（HDL）的Windows下VC的源代码，根据HDUMP修改的（改正了几处错误）。命令行方式执行，具体使用说明可在命令行中看到。HDP.exe是执行程序。-PS2 drive straight Irrigation (HDL) VC Windows source code According HDUMP amended (corrected several errors). Command-line approach to the implementation of specific use on the command line can be seen. HDP.exe implementation procedures.
Platform: | Size: 270336 | Author: 胡欢 | Hits:

[VHDL-FPGA-Verilog] crc_16

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
Platform: | Size: 31744 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] veriloghdl快速入门

Description: verilog hdl 快速入门,里面包含很多有用的硬件描述语言的程序-Verilog HDL Quick Start, which contains many useful hardware description language procedures
Platform: | Size: 371712 | Author: guo | Hits:

[Documents] HDL

Description:
Platform: | Size: 63488 | Author: xwca | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM_Core

Description: arm verilog hdl ip core-arm Verilog HDL core ip
Platform: | Size: 70656 | Author: lile | Hits:

[Other] chinese_version_Verilog_HDL_lecture

Description: 中文版Verilog HDL简明教程 第1章 简介 第2章 HDL指南 第3章 Verilog语言要素 第4章 表 达 式 第5章 门电平模型化 -Chinese version of Verilog HDL Concise Guide to Chapter 1 Introduction Chapter 2 HDL Guide, Chapter 3 Verilog language factor expression Chapter 4 Chapter 5 gate-level modeling
Platform: | Size: 88064 | Author: 王光辉 | Hits:

[VHDL-FPGA-Verilog] qep_data_bus

Description: 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的-address bus interface based on the four frequency signal encoder interface FPGA Verilog HDL
Platform: | Size: 1187840 | Author: 孙卓君 | Hits:

[Com Port] verilog_UART

Description: UART verilog hdl 实现-UART Verilog HDL achieve
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] taxi1

Description: 出租车计价器，简单、方便，采用verilog hdl语言编写，所用平台是MAXPLUS软件-Taximeter, simple, convenient, using Verilog HDL language, by using the platform of software Segments
Platform: | Size: 976896 | Author: zhz | Hits:
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