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[VHDL-FPGA-Verilog] verilog232423489

Description: verilog hdl教程135例，例子很好，对新学的很有帮助-verilog hdl Guide 135 cases, very good example of the new study helpful
Platform: | Size: 173056 | Author: 安安 | Hits:

[Embeded-SCM Develop] viterbi_decoder_sources_code_verilog

Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Platform: | Size: 44032 | Author: 林四昆 | Hits:

[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188416 | Author: 张驰 | Hits:

[VHDL-FPGA-Verilog] 1_061026140305

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.
Platform: | Size: 204800 | Author: | Hits:

[Embeded-SCM Develop] quartusGuide

Description: 设计输入 ! 多种设计输入方法 – Quartus II • 原理图式图形设计输入 • 文本编辑 – AHDL, VHDL, Verilog • 内存编辑 – Hex, Mif – 第三方工具 • EDIF • HDL • VQM – 或采用一些别的方法去优化和提高输入的灵活性: • 混合设计格式 • 利用LPM和宏功能模块来加速设计输入-design input! Design a variety of input methods-Quartus
Platform: | Size: 844800 | Author: fgghh | Hits:

[MPI] fifo_ver_131

Description: fifo verilog hdl 源程序-fifo verilog hdl source
Platform: | Size: 20480 | Author: zlw | Hits:

[Other] VerilogHDLcoding

Description: Verilog-HDL编写规范-非常全,非常适合初学者-Verilog-HDL prepared norms- all very, very suitable for beginners
Platform: | Size: 221184 | Author: dai hai bo | Hits:

[VHDL-FPGA-Verilog] memoryuse

Description: Verilog HDL语言在FPGA实现中的存储器的使用详细说明-Verilog HDL language in the FPGA memory of the use of detailed
Platform: | Size: 343040 | Author: 文俊 | Hits:

[VHDL-FPGA-Verilog] chap6

Description: 《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3
Platform: | Size: 2048 | Author: hutian | Hits:

[VHDL-FPGA-Verilog] taix_fee

Description: verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System
Platform: | Size: 553984 | Author: yukiflower | Hits:

[VHDL-FPGA-Verilog] 8251Verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
Platform: | Size: 15360 | Author: 钟兵 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi(auto)

Description: 用verilog hdl硬件描述语言实现多人抢答器功能，有计时，计分，报警等功能。-Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
Platform: | Size: 266240 | Author: 杨操 | Hits:

[VHDL-FPGA-Verilog] fft1024

Description: 1024点fft verilog hdl-1024-point fft verilog hdl
Platform: | Size: 24576 | Author: | Hits:

[MiddleWare] crc

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用verilog HDL编写-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared using verilog HDL
Platform: | Size: 1024 | Author: 宋子奇 | Hits:

[Software Engineering] Verilog_HDL

Description: Verilog HDL程序设计教程，非常实用，对学习Verilog非常有用。
Platform: | Size: 10857472 | Author: 汪毅 | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!
Platform: | Size: 53248 | Author: 小方 | Hits:

[Other] verilog_std

Description: Verilog HDL的标准，比较详细的语法说明-Verilog HDL standards, a more detailed description of the grammar
Platform: | Size: 1429504 | Author: 甲壳虫 | Hits:

[Other] TW-Verilog

Description: 台湾verilog hdl硬件描述性语言，适合有基础的人-Taiwan verilog hdl hardware description language, suitable for those who have the basis of
Platform: | Size: 1412096 | Author: josh915 | Hits:

[SCM] mcu_interface

Description: FPGA与单片机接口，用Verilog hdl写的，仿真波形正确。-FPGA and MCU interface, written using Verilog hdl, simulation waveform correctly.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
Platform: | Size: 211968 | Author: 杨轶帆 | Hits:
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