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[Other] BeiJingDaXue_verilog_PPT

Description: 数字集成电路设计入门 --从HDL到版图 于敦山 北大微电子学系 Verilog完整课件，是学习verilog HDL的很好的参考资料。 -Introduction to digital integrated circuit design- from the territory in HDL mts Microelectronics Department of Beijing University Verilog complete courseware, learning verilog HDL is a good reference.
Platform: | Size: 628736 | Author: hulin | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Platform: | Size: 162816 | Author: zx | Hits:

[VHDL-FPGA-Verilog] rece_7E

Description: HDLC控制接收数据开始标志7E和去零模块，用于FPGA与E1相接，Verilog HDL语言编写-HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language
Platform: | Size: 2048 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] 200759102123376

Description: Verilog HDL数字控制系统设计实例-Verilog HDL Digital Control System Design Example
Platform: | Size: 11976704 | Author: wphyl | Hits:

[VHDL-FPGA-Verilog] interleave

Description: 数据交织器 verilog HDL源文件-Data interleaver verilog HDL source file
Platform: | Size: 100352 | Author: 长空 | Hits:

[VHDL-FPGA-Verilog] Ultraedit_verilog

Description: 这个文件中提供了 verilog hdl 的在ultra edit32中编程所需要的语法-This document provides a verilog hdl in ultra edit32 programming required in grammar
Platform: | Size: 30720 | Author: 陈轩辕 | Hits:

[VHDL-FPGA-Verilog] AES_RTL

Description: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Platform: | Size: 15360 | Author: 林夢魔 | Hits:

[VHDL-FPGA-Verilog] sinwave

Description: 用verilog HDL产生正弦阶梯波。加da即可输出正弦波-Using verilog HDL ladder generated sine wave. Da can increase the output sine wave
Platform: | Size: 1024 | Author: chenmao | Hits:

[VHDL-FPGA-Verilog] liangzhu

Description: FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用，验证通过，工程环境为Altera Quartus II -Introduction to the Verilog HDL FPGA development process 2 --- Butterfly music player, the real available, verified by the project environment for the Altera Quartus II
Platform: | Size: 301056 | Author: renyong0801 | Hits:

[MiddleWare] Verilog_HDL

Description: Verilog HDL入门,学习的最好参考资料，可以极短的时间内学会-Introduction to Verilog HDL, learning the best reference materials, can be a very short time the Institute
Platform: | Size: 191488 | Author: 胡容华 | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Platform: | Size: 6144 | Author: 刘义春 | Hits:

[VHDL-FPGA-Verilog] I2C_Controller

Description: I2C控制器的源代码，Verilog HDL语言编写，可以直接调用-I2C controller source code, Verilog HDL language, you can directly call
Platform: | Size: 2048 | Author: zw | Hits:

[VHDL-FPGA-Verilog] BLDCM

Description: verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation
Platform: | Size: 199680 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] VERILOGHDLlanguage

Description: verilog HDL语言，对于超大规模集成电路开发学习非常有好处-verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning
Platform: | Size: 2928640 | Author: 付天 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS调试心得,VERIOLG 各HDL和VHDL语言的DDS调试方法-DDS debugging experience, VERIOLG the HDL and VHDL languages DDS debugging method
Platform: | Size: 53248 | Author: 李达兴 | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
Platform: | Size: 5120 | Author: 阿明 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: verilog hdl 综合实用教程，一本非常实用易学易懂的书-verilog hdl Comprehensive practical tutorial, a very useful book to learn to understand
Platform: | Size: 2528256 | Author: 管清宇 | Hits:

[Books] Hardware_Description_Language_Verilog(Version4).ra

Description: 中文名称为：硬件描述语言 Verilog（第四版）。讲解verilog HDL的经典图书。Thomas和Moorby编著，内容涵盖了:行为建模、并发进程、逻辑级建模、高级时序、逻辑综合、行为综合等方面的内容。通读此书后，不需要再读其他的verilog书籍。-Chinese name is: Hardware Description Language Verilog (Fourth Edition). Verilog HDL on classic books. Thomas and Moorby authoring, content covers: behavioral modeling, concurrent process, logic-level modeling, advanced timing, logic synthesis, behavior and other aspects of integrated content. After reading this book, do not need to read other books of Verilog.
Platform: | Size: 5331968 | Author: 王敏 | Hits:

[Other] cpld11245

Description: 主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率 测量的优点 同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频 模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等 主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设 计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要 求。-Introduced, such as the accuracy of frequency measurement principle, the principle has in the entire test frequency to maintain the advantages of high precision frequency measurement at the same time the basis of the principle of using the Verilog HDL language, such as the design of a high-speed precision frequency measurement module, and use of EDA Development platform QUARTUS11 3 .0 on CPLD chip to write, and achieved a count of the main logic function, such as the use of C language is also designed such precision the frequency of control procedures to enhance measurement accuracy. This design achieved a wide range of frequency changes in signal frequency measurement, to meet the high-speed, high precision frequency measurement requirements.
Platform: | Size: 320512 | Author: zhengwei | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
Platform: | Size: 425984 | Author: 盼盼 | Hits:
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