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Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
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Size: 79872 |
Author: sundan |
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Description: Verilog HDL 华为入门教程.pdf
内部资料-Verilog HDL Tutorial Huawei. Pdf internal information
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Size: 263168 |
Author: 李天 |
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Description: Verilog HDL语言设计的交通灯设计-Verilog HDL language designed traffic light design
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Size: 312320 |
Author: yyfeng |
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Description: 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
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Size: 211968 |
Author: zbs |
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Description: Verilog HDL的程式，上網找到SPI程式，
vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v!
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Size: 145408 |
Author: Rick |
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Description: Verilog HDL语言练习与讲解 里面有很多实用的源代码-Verilog HDL language exercises on the inside and have a lot of useful source code
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Size: 265216 |
Author: 李晓东 |
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Description: Verilog HDL 华为入门教程-网络上比较经典的学习资料-Verilog HDL Tutorial Huawei- Network Learn more classical information
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Size: 263168 |
Author: yu binbin |
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Description: Verilog HDL的入门书籍，老外写的，语言简洁，是快速掌握Verilog编程的好教材，大家可以学习下-Verilog under the principle of serial communication, including receiving and sending the code. Through simulation, are a good example of Verilog study.
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Size: 5348352 |
Author: clins |
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Description: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
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Size: 5120 |
Author: 镜子 |
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Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
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Size: 1603584 |
Author: shsh |
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Description: 基于Verilog HDL的SPI代码，可在FPGA上实现SPI接口，请大家参考-Verilog HDL based on the SPI code, implementation in FPGA on SPI interface, please refer to
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Size: 1024 |
Author: treefan.liang |
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Description: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
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Size: 1244160 |
Author: chenlu |
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Description: 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
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Size: 774144 |
Author: 孟霑 |
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Description: 华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.
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Size: 34816 |
Author: 张芸 |
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Description: 基于Verilog HDL的16位超前进位加法器
分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
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Size: 7168 |
Author: 韩伟 |
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Description: verilog HDl 交通灯的实现,而且这是有别于一般的vhdl语言-verilog HDl traffic light
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Size: 324608 |
Author: 萧海武 |
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Description: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
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Size: 12288 |
Author: 孟军 |
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Description: Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.
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Size: 40601600 |
Author: liuxing |
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Description: 北航Verilog教程.
Verilog HDL基本结构
数据类型及常量、变量
运算符及表达式
语句
赋值语句和块语句
条件语句
...
-BUAA Verilog Tutorial. Verilog HDL data types and the basic structure of constants, variables and expression operator assignment statements and conditional statements statement block ...
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Size: 2350080 |
Author: 黄虎 |
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Description: 用Verilog HDL编写的秒表设计，可以实现百分之一秒，十分之一秒，秒，十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
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Size: 6144 |
Author: maylag |
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