FIFO_8_8 FIFO FIFO queue, a cache, or a pipeline, - CodeBus

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VHDL-FPGA-Verilog

Title: FIFO_8_8

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
5kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
plyx2003_007

Description: FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)

Downloaders recently: [More information of uploader plyx2003_007]

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File list (Check if you may need any files):

FIFO_8_8
........\cmp_state.ini
........\db
........\..\FIFO_8_8.db_info
........\..\FIFO_8_8.eco.cdb
........\..\FIFO_8_8.sld_design_entry.sci
........\FIFO_8_8.qpf
........\FIFO_8_8.qsf
........\FIFO_8_8.qws
........\FIFO_8_8.v
说明.txt

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