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[Mathimatics-Numerical algorithms] 数字边沿鉴相器.zip

Description:
Platform: | Size: 8496 | Author: | Hits:

[Embeded-SCM Develop]  148个verilog hdl小程序（有很多testbench）——.rar

Description:
Platform: | Size: 55801 | Author: | Hits:

[Embeded-SCM Develop] 91516677.zip

Description:
Platform: | Size: 3360 | Author: | Hits:

[Embeded-SCM Develop] uart 源码 (VHDL).zip

Description:
Platform: | Size: 10750 | Author: | Hits:

[Embeded-SCM Develop] spicore.zip

Description:
Platform: | Size: 13587 | Author: | Hits:

[Embeded-SCM Develop] crc_verilog_xilinx.zip

Description:
Platform: | Size: 10439 | Author: | Hits:

[Other resource] rtl

Description: 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
Platform: | Size: 93845 | Author: 刘吉 | Hits:

[Other resource] 结合XILINXCPLD RS232通信(verilog)

Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: | Size: 122378 | Author: 于飞 | Hits:

[Other resource] 能综合的YCrCb2RGB模块（verilog)_采用3级流水线

Description: 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
Platform: | Size: 1080 | Author: 于飞 | Hits:

[Other] FFT16

Description: 基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA
Platform: | Size: 2282 | Author: lsd | Hits:

[Other resource] atahost_wb_slave

Description: 硬盘控制程序代码 硬盘控制器代码编写，可以直接使用-drive control code prepared hard disk controller code can be used directly! !
Platform: | Size: 4144 | Author: 小的于 | Hits:

[Other resource] CORDIC

Description: 用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
Platform: | Size: 4108 | Author: diskmps | Hits:

[Other resource] and_or

Description: veilog 代码 用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.
Platform: | Size: 3531 | Author: 宋昆仑 | Hits:

[Other resource] arbit

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 5886 | Author: 宋昆仑 | Hits:

[Other resource] backward

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 3387 | Author: 宋昆仑 | Hits:

[Other resource] bidir

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 3856 | Author: 宋昆仑 | Hits:

[Other resource] bin2gry

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 4092 | Author: 宋昆仑 | Hits:

[Other resource] Verilog_EXAMPLE

Description: DesignWave 2005 8 Verilog Example -Design Wave Verilog Example
Platform: | Size: 383347 | Author: sky | Hits:

[Other resource] alu64_struct

Description: 六十四位ALU设计源代码，可实现加减，逻辑与，或等多种功能。-64 ALU design source code can be modified to achieve, and logic, or other functions.
Platform: | Size: 1208 | Author: 李宁 | Hits:

[Crack Hack] MD5(verilog)

Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Platform: | Size: 4806 | Author: 张雷 | Hits:
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