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Description: DE2_Top.rar，做好了的IP核，大家开来下啊！-DE2_Top.rar, do a good job of the IP core, open to everyone under ah!
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Size: 19820 |
Author: zhan |
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Description: 基于fpga的MJPEG编码,用硬件描述语言vlogic写的-they simply based on the JPEG coding, using hardware description language to write the vlogic
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Size: 10059 |
Author: xiao |
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Description: 计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
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Size: 272065 |
Author: 周颖 |
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Description: 从Xilinx网站上下的，学习FPGA部分动态重配置很好的例子。-from across the Xilinx website, learning some FPGA dynamic reconfigurable good example.
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Size: 2554642 |
Author: sk |
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Description: rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流
-rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
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Size: 15641 |
Author: niepan |
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Description: 一个用max+plus II写的很小的源码。简单但对初学还行吧-max plus one with a small II was the source. Simple but for beginners it is also OK
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Size: 926 |
Author: 风 |
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Description: 百兆以太网mac和mii的vhdl源程，作IPcore的时候非常有用-Fast Ethernet MII and the VHDL source way for IPcore very useful when
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Size: 124437 |
Author: 王前 |
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Description: Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
Platform: |
Size: 1521 |
Author: lzy |
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Description: 采用LRU替换算法。这种算法选择最久没有被访问的块作为被替换的块。
为了实现LRU算法，要在块表中为每一块设置一个计数器（cnt0，cnt1，cnt2，cnt3，）。计数器的长度为2位。-using LRU replacement algorithm. This algorithm to choose the most long visit is not being replaced as a block by block. To achieve LRU algorithm, in block form for each one to set up a Counter (cnt0, cnt1. cnt2, cnt3,). To counter the length of two.
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Size: 1546 |
Author: wangjiao |
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Description: mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
Platform: |
Size: 26110 |
Author: cray |
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Description: 状态机得用法，可以帮助新手了解状态机得用法以及掌握用途-state machine in use, and can help newcomers understand the state machine in use, and control purposes
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Size: 2390 |
Author: andyxm |
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Description: 基于ＡＬＴＥＲＡ公司的ＤＥ２的ＬＣＤ显示程序，一起学习．非常好的资料，也非常难得．是我参加培训时所得-the DE2 LCD display program, learning together. Very good information, and they are extremely rare. I receive training
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Size: 5858 |
Author: 唐老鸭 |
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Description: USB 1.1 PHY的代码，verilog语言
USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
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Size: 8753 |
Author: william |
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Description: 随机序列发生器,是一个m序列,生成函数都写在里面,位宽为4,可以改变!-random sequence generator, m is a sequence, generating function will be included in the inside, for four bit-can be changed!
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Size: 117793 |
Author: lw234620 |
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Description: 交织器的一部分,可以生成交织索引函数,如果加上一个随即序列发生器就可以组成一个交织器 了!-interleaver part of the index can be generated intertwined function, If coupled with a sequence generator immediately on the formation of a interleaver!
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Size: 1757 |
Author: lw234620 |
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Description: 复接程序,用quartus运行的,可以把很多个信号复接在一起,是程序的一部分!-Multiplexing procedures used quartus operations, can put a lot of signal multiplexing together, is part of that process.
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Size: 170262 |
Author: lw234620 |
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Description: 是用verilog写的,解复接程序,可以把复接的反过来,一般用在解码程序中!-verilog is written, Demultiplexer procedures can multiplexing the contrary, generally used in the decoding process.
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Size: 163341 |
Author: lw234620 |
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Description: 用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!-verilog prepared using the procedures used to calculate the error rate. the encoding and decoding process used in the!
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Size: 184708 |
Author: lw234620 |
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Description: pc104接口的verilog代码，仅供参考-pc104 verilog interface code for reference purposes only
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Size: 1008 |
Author: sunlee |
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Description: the verilog model of sdram-mt48lc2m32b2 device.-the verilog model of sdram - mt48lc2m32b2 d evice.
Platform: |
Size: 6802 |
Author: nightyboy |
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