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Description: 一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!
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Size: 3351 |
Author: 李全 |
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Description: 高品质音频编解码器WM8731的Verilog使用程序。-high-quality audio codec WM8731 Verilog procedures.
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Size: 7314 |
Author: 李全 |
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Description: 用verilog HDL 语言写的在显示器上显示图案的源程序-with Verilog HDL language written on display in the pattern of the source
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Size: 179789 |
Author: yhr |
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Description: 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
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Size: 424058 |
Author: yhr |
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Description: FPGA/CPLD应用,uart通讯VHDL原码.-FPGA / CPLD applications, UART communications VHDL source.
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Size: 11063 |
Author: cyberworm |
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Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source
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Size: 10421 |
Author: cyberworm |
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Description: ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the waveform window or window List View, it will also compare the results generate a text file
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Size: 3798 |
Author: cyberworm |
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Description: CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
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Size: 221251 |
Author: 李文文 |
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Description: Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
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Size: 1530 |
Author: wyl |
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Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
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Size: 2015 |
Author: wyl |
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Description: 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
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Size: 822 |
Author: dandan |
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Description: 比较完善的CRC编码VerilogHDL描述-more perfect description of CRC coding VerilogHDL
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Size: 4640 |
Author: nil |
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Description: 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL description
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Size: 4855 |
Author: nil |
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Description: 多通道的ACC设计VeerilogHDL描述-multi-channel design VeerilogHDL ACC Description
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Size: 7938 |
Author: nil |
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Description: 各种门电路模型的VerilogHDL描述-various gates model of Verilog HDL description
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Size: 2261 |
Author: nil |
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Description: 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL description
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Size: 2822 |
Author: nil |
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Description: Verilog变成100例，里面包含了Verilog编程中常见的一些例子，对于新手还是很有帮助的。-Verilog into 100 cases, they include a Verilog Programming common examples is very helpful for the novice.
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Size: 43949 |
Author: 张存飞 |
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Description: //led.v
/*-------------------------------------
LED显示模块：led(CLK,AF,ADDR,DATA)
功能： 显示
注意事项： 8位LED
参数： CLK:扫妙时钟输入，推荐1kHz
AF:数码管输出，a～h
ADDR:数码管选择位数出，0~2
DATA:显示数据输入0~9999 9999
编写人： 黄道斌
编写日期： 2006/07/13
-------------------------------------*/-/ / led.v /*--------------------------- ---------- LED Display Module : led (CLK, AF, ADDR. DATA) function : to show : 8 LED parameters : CLK : So Wonderful clock input, Suggest 1kHz AF : digital tube output, a ~ h ADDR : digital control options from the median, 0 ~ 2 DATA : data show that the importation of 0 ~ 9999 9999 prepared : Huang Daobin preparation date : 2006/07/13 ------------------------------ -------*/
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Size: 1746 |
Author: 黄道斌 |
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Description: sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
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Size: 1206 |
Author: kevin |
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Description: DE2_i2sound.rar，大家快来下啊，做好了的IP核-DE2_i2sound.rar, everyone is breaking under ah, do a good job of the IP Core
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Size: 27772 |
Author: zhan |
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