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Description: SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
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Size: 1658 |
Author: 洪戈 |
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Description: 实用闹钟的verilog代码。不是vhdl的！经过ldv验证-practical alarm the Verilog code. VHDL is not! After certification ldv
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Size: 4206 |
Author: 徐哦俄 |
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Description: 计算器芯片的verilog实现代码！
时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
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Size: 6261 |
Author: 徐哦俄 |
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Description: Systemverilog 编写的贩卖机代码-Systemverilog preparation for the sale code
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Size: 7445 |
Author: 开开 |
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Description: vhdl实例教程，其中的例子适合新手演示使用，肯定会有帮助的。-VHDL example tutorial, an example of the use for novice demo, it will certainly help.
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Size: 779835 |
Author: ghjghj |
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Description: 交通灯信号的ｆｐｇａ实现。通过ｖｅｒｉｌｏｇ语言编程，在ｆｐｇａ上调试通过。-traffic signal lights they simply achieve. Through the Verilog language programming, they simply passed on debugging.
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Size: 948 |
Author: 王海 |
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Description: 以verilog HDL 语言编写的一首歌曲，可供初学者借鉴-to Verilog HDL language of a song, draw for beginners
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Size: 951 |
Author: 王海 |
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Description: 用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能-using HDL to write electronic calendar, it shows the year, month, day and time, with alarm function
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Size: 1785632 |
Author: zz |
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Description: 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
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Size: 595105 |
Author: 大圣 |
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Description: 用HDL语言编写的通用fifo源码，通过对fifo的宽度和深度进行配置，可以产生我们所需要的fifo，还包括fifo的测试程序和仿真Makefile脚本-with HDL prepared by the General fifo source, fifo of the breadth and depth configuration, can produce what we need fifo. also included fifo testing procedures and simulation scripts Makefile
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Size: 26405 |
Author: 崔崔 |
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Description: 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
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Size: 62383 |
Author: 王椿棠 |
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Description: 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行
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Size: 2205 |
Author: modelsims |
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Description: veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
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Size: 436406 |
Author: 陶玉辉 |
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Description: 甚短距离互联（Veryshort reach VSR）协议编成实现-very short distance from the Internet (Veryshort reach VSR) composition to achieve agreement
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Size: 14389 |
Author: 葛琳 |
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Description: 在公司做的一个用FPGA实现的数字电视系统中
ASI转TS流的程序-done in the company of an FPGA using the digital television system to ASI TS flow procedures
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Size: 3722 |
Author: 无朝 |
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Description: 带分频器的bcd计数电路设计，verilog源码-dividers with the bcd count circuit design, Verilog source
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Size: 292676 |
Author: 倪璠 |
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Description: Arbiter.v verilog实现
三路请求，使用循环策略的仲裁器
含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
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Size: 1956 |
Author: 夏虫 |
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Description: 该源码实现了一个8*8位的乘法器，在实现的过程中用到了宏单元-the source to achieve an 8 * 8 Multiplier that in the process modules used Acer
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Size: 341884 |
Author: 倪璠 |
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Description: 用VERLOG实现交通灯程序，有红绿两种灯，绿灯到红灯，路灯闪10秒，可以调整红绿灯持续时间-VERLOG achieve with traffic lights procedures, two black lights, the green light to red lights, flashing lights for 10 seconds, can be adjusted duration of traffic lights
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Size: 965 |
Author: 王天 |
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Description: 这也是8255的设计,不知道是否好使,希望得到验证-This is 8255 in the design, so I do not know whether the hope of gaining certification
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Size: 278334 |
Author: runclever |
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