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Description: FIFO先入先出堆栈，包括三个子程序，可根据需要选择-FIFO first in-first stack, including three subprogram, according to choose
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Size: 4799 |
Author: 陈正一 |
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Description: Verilog HDL 程序
双路脉冲发生器的代码
包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块
是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is written I hope to help you, it can be mail : shaojunwu1@163.com
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Size: 4210 |
Author: 邵君武 |
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Description: NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
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Size: 1637 |
Author: 黄建生 |
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Description: NIOS环境PWM的USER LOGIC实例3-NIOS environment PWM USER Logic Example 3
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Size: 2340 |
Author: 黄建生 |
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Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
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Size: 39048 |
Author: wl |
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Description: CFAH1602BNYAJP液晶的fpga控制程序-CFAH1602BNYAJP they simply control procedures
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Size: 2377 |
Author: 陈世利 |
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Description: uart d的verilog 程序，可以实现普通串口功能-UART d Verilog procedures can be achieved ordinary serial port function
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Size: 5419 |
Author: 梁启 |
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Description: 16450异步通讯接口，ALDEC提供，修正版（由网友zhy修改，修正一些错误-16450 asynchronous communications interface, providing ALDEC, the revised version (from netizens. Changes amendments to some errors
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Size: 7024 |
Author: 梁启 |
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Description: CRC校验码，用于对数据流进行crc校验。
主要有CRC_16,CRC_8,CRC_32校验。
所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
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Size: 10947 |
Author: 李鹏 |
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Description: Verilog 的交通灯的例子。源代码中有详细的注释。-Verilog traffic lights examples. The source code for detailed comments.
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Size: 123720 |
Author: 徐勇 |
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Description: VHDL编程
: out std_logic
-- Transmitter control
DataBits : in std_logic_vector(1 downto 0)
StopBits : in std_logic_vector(1 downto 0)
ParityEnable: in std_logic
ParityEven : in std_logic
ParityStick : in std_logic
TxBreak : in std_logic
-- Transmitter status
THRE : out std_logic -VHDL programming : out std_logic -- Transmitter control DataBits : in std_logic_vector (a DOWNTO 0) StopBits : in std_logic_vector (a DOWNTO 0) ParityEnable : in std_logic ParityEven : in std_logic ParityStick : in std_logic TxBreak : in std_logic -- Transmitter status THRE : out std_logic
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Size: 18460 |
Author: 谢强 |
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Description: systemverilog编写的cpu读写mem程序-SystemVerilog prepared by the cpu readers mem procedures
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Size: 1017 |
Author: 王晓波 |
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Description: systemverilog编写的fifo例子-SystemVerilog examples prepared by the fifo
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Size: 923 |
Author: 王晓波 |
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Description: 4bit ALU 利用vhdl语言编写的4位ALU
开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
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Size: 18290 |
Author: bob |
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Description: sale，自动收获机。首先投币，然后买东西，然后退币-sale, automatic harvester. The first coin, and then buy something, and then coin
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Size: 1217 |
Author: 杨小坤 |
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Description: 11,13,16位超前进位加法器的Verilog HDL源代码。-11,13,16-CLA for the Verilog HDL source code.
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Size: 4121 |
Author: 周金喜 |
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Description: uart 通用异步接受机 编译环境为quartus-UART Universal Asynchronous Receiver and build environment for Quartus
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Size: 197052 |
Author: 雷鸣 |
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Description: Traffic light written with Verilog-written with Verilog
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Size: 1002694 |
Author: 吴意曦 |
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Description: mining source code written in Verilog
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Size: 21116 |
Author: 吴意曦 |
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Description: SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
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Size: 9869 |
Author: 洪戈 |
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