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[Other resource] UART_BooQuai

Description: FPGA上实现UART串口原程序，在ISE6编写的-FPGA serial UART to achieve the original procedure, the preparation of the ISE6
Platform: | Size: 11624 | Author: 樊 | Hits:

[Other resource] collectionOfImageAndinterpolation

Description: 该系统是一个实现图像数据采集以及对图像数据的插值处理，供其它系统进一步处理或显示的系统。具有一定的通用性，适合大多数CMOS图像传感器接入。1准确、适时的数据采集，尽量减少延迟 2采集模块具备一定的数据缓冲功能 3快速有效的数据插值 4使用较少的逻辑器件和存储器 5代码的可读性要强 -The system is a realization of image data acquisition and the image data interpolation, other system for further processing or display system. Have certain common, for most CMOS image sensor access. An accurate and timely data collection, to minimize delay in two modules have some data buffering function three rapid and effective use of data interpolation four less logic five memory devices and readability of the code stronger
Platform: | Size: 2662540 | Author: 矫渊培 | Hits:

[Other resource] FIR_1

Description: FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
Platform: | Size: 950 | Author: 李甫 | Hits:

[Windows Develop] xapp195

Description: signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
Platform: | Size: 7535 | Author: ldy | Hits:

[Other resource] sdramcore

Description: sdram控制的内核，高手编的，已经调试过了，没有错误-SDRAM control of the kernel, the top series, has been tuned, no errors
Platform: | Size: 20198 | Author: 韩 | Hits:

[Video Capture] sram_verilog

Description: 告诉图形采集 verilog代码 很简单的 第一次发-tell graphics Acquisition Verilog code is very simple first grant
Platform: | Size: 222708 | Author: 徐常志 | Hits:

[Other resource] color_space_converter

Description: verlog 编程 色彩空间转换 有测试文档-verlog programming color space conversion is testing documents
Platform: | Size: 8762 | Author: 周信均 | Hits:

[Other resource] ad_DCT

Description: verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
Platform: | Size: 33663 | Author: 周信均 | Hits:

[Other resource] entropy_coding

Description: 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His description of coding (entropy coding) for image compression test files are encoded
Platform: | Size: 19701 | Author: 周信均 | Hits:

[Other resource] run_length_coding

Description: 用verilog 编写 应用于图像压缩编码中 使用行程长度编码(run lengthencoding,RLE)对交流系数(Aa)进行编码。-using Verilog prepared for image compression coding using length encoding (run leng thencoding, RLE) on the exchange coefficient (Aa) coding.
Platform: | Size: 9482 | Author: 周信均 | Hits:

[Other resource] verilog_jpeg

Description: 用verilog 描写 应用于数字图像压缩系统--jpeg 有测试文档-using Verilog description applied to digital image compression system -- a test jpeg files
Platform: | Size: 9152 | Author: 周信均 | Hits:

[Other resource] PCIarbitration

Description: 这是PCI 仲裁机制的VHDL源码，它实现了PCI仲裁机制。-PCI arbitration mechanism VHDL source code, it achieved a PCI arbitration mechanism.
Platform: | Size: 3753 | Author: 赵云 | Hits:

[Crack Hack] desimplementation

Description: 一个关于DES算法的verilog语言实现,包括了各个实现模块以及测试模块-a DES algorithm on the Verilog language, including the realization of the various modules and test modules
Platform: | Size: 17534 | Author: xkl | Hits:

[Other resource] VLSIrtl_spi

Description: verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.-Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.
Platform: | Size: 46104 | Author: citybus | Hits:

[Other resource] pcirtl

Description: 用verilog编写的pci——rtl级。-using Verilog prepared by the pci -- rtl level.
Platform: | Size: 197773 | Author: 程 | Hits:

[Other resource] 7led

Description: 7段发光二极管vhdl程序，可以验证led的fpga验证程序-seven of the light-emitting diode VHDL procedures can verify they simply led to the certification process
Platform: | Size: 283088 | Author: 马永涛 | Hits:

[Other resource] buzz

Description: 一个用vhdl语言编成的可以让蜂鸣器发声的的程序。-with a monument of the VHDL language allows the buzzer of the procedure.
Platform: | Size: 120812 | Author: 马永涛 | Hits:

[Other resource] clockbyvhdl

Description: 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
Platform: | Size: 27680 | Author: 马永涛 | Hits:

[Other resource] pwmvhdl

Description: 一个在xilinx的ise环境下编译仿真成功的pWM程序。-one of the Xilinx environment ideally compiler pWM success of the simulation procedures.
Platform: | Size: 136735 | Author: 马永涛 | Hits:

[Other resource] keybyise

Description: 一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。-a company embarks on the environment and ideally compile successful simulation keyboard operations.
Platform: | Size: 97333 | Author: 马永涛 | Hits:
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